公开(公告)号：US12293803B2

公开(公告)日：2025-05-06

申请号：US17943706

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Chad B. Erickson ,  Danilo Caraccio

IPC: G11C16/04 ,  G11C29/10 ,  G11C29/12 ,  G11C29/38

Abstract: Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.

公开(公告)号：US12235722B2

公开(公告)日：2025-02-25

申请号：US18216160

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US20240411451A1

公开(公告)日：2024-12-12

申请号：US18808341

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10

Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

公开(公告)号：US12079513B2

公开(公告)日：2024-09-03

申请号：US17657870

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.

公开(公告)号：US20240007265A1

公开(公告)日：2024-01-04

申请号：US18215479

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolò Izzo ,  Marco Sforzin

IPC: H04L9/06 ,  H04L9/32 ,  G06F21/64

CPC classification number: H04L9/0618 ,  H04L9/32 ,  G06F21/64

Abstract: A memory system can be provided with error detection capabilities at various levels and authentication and integrity check capabilities in parallel with data security schemes. The error detection capabilities can check for any errors not only on data paths within a memory controller, but also on data stored in memory devices. The authentication capabilities provided in parallel with the data security schemes can ensure/strengthen data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

公开(公告)号：US20230297285A1

公开(公告)日：2023-09-21

申请号：US18121874

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US11742002B2

公开(公告)日：2023-08-29

申请号：US17550535

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/22

CPC classification number: G11C7/1048 ,  G11C7/222 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

公开(公告)号：US11693781B2

公开(公告)日：2023-07-04

申请号：US16947851

申请日：2020-08-20

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Daniele Balluchi

IPC: G06F12/0866

CPC classification number: G06F12/0866 ,  G06F2212/311 ,  G06F2212/7201

Abstract: A processing device in a memory system receives, from a host system, a read command comprising an indication of a sub-region of a logical address space of a memory device. The processing device increments a counter associated with a region of the logical address space, the region comprising a plurality of sub-regions including the sub-region, the counter to track a number of read operations performed on the plurality of sub-regions of the region, wherein the counter is periodically decremented in response to an occurrence of a recency event on the memory device. The processing device further determines whether a value of the counter satisfies a cacheable threshold criterion and, responsive to the value of the counter satisfying the cacheable threshold criterion, sends, to the host system, a recommendation to activate the sub-region.

公开(公告)号：US11687273B2

公开(公告)日：2023-06-27

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

公开(公告)号：US20220199129A1

公开(公告)日：2022-06-23

申请号：US17550535

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.