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    Method to construct 3D devices and systems
    101.
    发明授权
    Method to construct 3D devices and systems 有权

    公开(公告)号：US11158598B1

    公开(公告)日：2021-10-26

    申请号：US17372476

    申请日：2021-07-11

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L21/30 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.

    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES
    102.
    发明申请
    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES 有权

    公开(公告)号：US20210242227A1

    公开(公告)日：2021-08-05

    申请号：US17235879

    申请日：2021-04-20

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H01L27/11556 ,  H01L29/78 ,  H01L27/11582 ,  G11C5/06

    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.

    METHOD TO CONSTRUCT 3D DEVICES AND SYSTEMS
    103.
    发明申请
    METHOD TO CONSTRUCT 3D DEVICES AND SYSTEMS 有权

    公开(公告)号：US20210233901A1

    公开(公告)日：2021-07-29

    申请号：US17214883

    申请日：2021-03-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L25/18 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a memory control on top; and then thinning the memory control, transferring a first memory wafer on top; and then thinning the first memory wafer; and then transferring a second memory wafer on top; and then thinning the second memory wafer. A 3D device, the device including: a first stratum including first bit-cell memory arrays; a second stratum including second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the first stratum overlays the third stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES
    104.
    发明申请
    3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES 有权

    公开(公告)号：US20210098490A1

    公开(公告)日：2021-04-01

    申请号：US17099706

    申请日：2020-11-16

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C7/18 ,  H01L29/423

    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.

    SEMICONDUCTOR DEVICE AND STRUCTURE WITH THERMAL ISOLATION
    109.
    发明申请
    SEMICONDUCTOR DEVICE AND STRUCTURE WITH THERMAL ISOLATION 审中-公开

    公开(公告)号：US20190057959A1

    公开(公告)日：2019-02-21

    申请号：US16166112

    申请日：2018-10-21

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L25/18 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

    Abstract: A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m·K thermal conductivity.

    SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    110.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE 审中-公开
    半导体存储器件和结构

    公开(公告)号：US20170053906A1

    公开(公告)日：2017-02-23

    申请号：US15243941

    申请日：2016-08-22

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H01L27/06 ,  H01L29/161 ,  H01L27/115 ,  H01L27/108 ,  H01L27/24 ,  H01L23/528 ,  H01L27/102

    CPC classification number: H01L27/11578 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H01L29/749

    Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

    Abstract translation: 一种装置，包括：包括第一存储单元的第一结构，所述第一存储单元包括第一晶体管; 以及包括第二存储器单元的第二结构，所述第二存储单元包括第二晶体管，其中第二晶体管覆盖第一晶体管，以及多个存储单元控制线，其中第一晶体管与第二晶体管自对准，其中 第二晶体管的第二晶体管沟道与第一晶体管的第一晶体管沟道对准，如同由外延生长工艺所产生的那样，对准的原子水平处于原子水平。

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