公开(公告)号：US20160225436A1

公开(公告)日：2016-08-04

申请号：US14611056

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Niladri Narayan Mojumder ,  Jonathan Liu ,  Choh Fei Yeap

IPC: G11C11/417 ,  G06F11/07

CPC classification number: G11C11/417 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.

Abstract translation: 对于多个工作频率的每个工作频率，存储器件的操作方法包括确定电源电压的目标电压电平。 例如，确定用于多个工作频率的第一工作频率的第一目标电压电平。 该方法包括当存储器件在第一工作频率下操作并由具有第一电压电平的电源供电时从存储器件存取第一数据。 该方法包括确定与第一数据相关联的第一数量的错误。 该方法还包括响应于满足阈值的第一数量的误差，将电源电压调整到大于第一电压电平的第二电压电平。

公开(公告)号：US09336864B2

公开(公告)日：2016-05-10

申请号：US14473974

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/405 ,  G11C11/409

CPC classification number: G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

Abstract translation: 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

公开(公告)号：US20160064068A1

公开(公告)日：2016-03-03

申请号：US14473974

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

Abstract translation: 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

公开(公告)号：US09257407B2

公开(公告)日：2016-02-09

申请号：US14064944

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Narayan Mojumder

IPC: H01L27/092 ,  H01L23/00 ,  H01L23/528 ,  H01L29/267 ,  H01L21/822 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/762

CPC classification number: H01L24/29 ,  H01L21/76251 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/528 ,  H01L24/83 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/267 ,  H01L2224/83948 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.

Abstract translation: 将异质沟道材料集成到半导体器件中的方法以及集成异构沟道材料的半导体器件。 一种制造半导体器件的方法包括以第一热预算处理第一材料的第一衬底以制造p型器件。 该方法还包括将第二材料的第二衬底耦合到第一衬底。 该方法还包括处理第二基板以在小于第一热预算的第二热预算下制造n型装置。 p型设备和n型设备可以协作以形成互补设备。

公开(公告)号：US09236483B2

公开(公告)日：2016-01-12

申请号：US14179311

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Pr Chidambaram ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/66 ,  H03K17/687

CPC classification number: H01L29/7855 ,  H01L29/0607 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H03K17/687 ,  H03K2017/6878 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract translation: 在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。 阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。 后门提供改进的电流控制。 由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。

公开(公告)号：US20150035072A1

公开(公告)日：2015-02-05

申请号：US13958646

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7833 ,  H01L2924/0002 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/432 ,  H03F2203/7209 ,  H03F2203/7236 ,  H01L2924/00

Abstract: A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band.

Abstract translation: 一种方法包括在晶片的第一区域和第二区域中形成第一栅极氧化物。 该方法还包括执行第一处理以在第二区域中形成第二栅极氧化物。 第二栅极氧化物具有与第一栅极氧化物不同的厚度。 该方法还包括在第一区域中形成第一器件的第一栅极材料并在第二区域中形成第二器件的第二栅极材料。 第一设备对应于第一射频（RF）频带，第二设备对应于与第一RF频带不同的第二RF频段。