MEMORY DEVICE WITH ADAPTIVE VOLTAGE SCALING BASED ON ERROR INFORMATION
    101.
    发明申请
    MEMORY DEVICE WITH ADAPTIVE VOLTAGE SCALING BASED ON ERROR INFORMATION 有权
    基于错误信息的具有自适应电压调节的存储器件

    公开(公告)号:US20160225436A1

    公开(公告)日:2016-08-04

    申请号:US14611056

    申请日:2015-01-30

    Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.

    Abstract translation: 对于多个工作频率的每个工作频率,存储器件的操作方法包括确定电源电压的目标电压电平。 例如,确定用于多个工作频率的第一工作频率的第一目标电压电平。 该方法包括当存储器件在第一工作频率下操作并由具有第一电压电平的电源供电时从存储器件存取第一数据。 该方法包括确定与第一数据相关联的第一数量的错误。 该方法还包括响应于满足阈值的第一数量的误差,将电源电压调整到大于第一电压电平的第二电压电平。

    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE
    103.
    发明申请
    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE 有权
    SILICON GERMANIUM读端口,用于静态随机存取存储器寄存器文件

    公开(公告)号:US20160064068A1

    公开(公告)日:2016-03-03

    申请号:US14473974

    申请日:2014-08-29

    Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

    Abstract translation: 静态随机存取存储器(SRAM)电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗(SiGe)沟道的第一p型金属氧化物半导体(PMOS)晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管,其中第二PMOS晶体管耦合到第一PMOS晶体管。

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