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公开(公告)号：US11630788B2
公开(公告)日：2023-04-18
申请号：US16921061
申请日：2020-07-06
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Ian P. Shaeffer , John Eble
Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
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公开(公告)号：US20220247547A1
公开(公告)日：2022-08-04
申请号：US17676425
申请日：2022-02-21
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe
Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
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公开(公告)号：US11165613B2
公开(公告)日：2021-11-02
申请号：US16256882
申请日：2019-01-24
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz , Vladimir Stojanovic
IPC: H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
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104.发明授权公开(公告)号：US11115247B2
公开(公告)日：2021-09-07
申请号：US16885948
申请日：2020-05-28
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03 , H01J37/00 , H01L21/311 , H01L21/67 , H01L21/683 , H01L21/768 , H01L29/66
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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公开(公告)号：US11063791B2
公开(公告)日：2021-07-13
申请号：US16714178
申请日：2019-12-13
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
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Patent Agency Ranking
公开(公告)号：US10812297B2
公开(公告)日：2020-10-20
申请号：US16841385
申请日：2020-04-06
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
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公开(公告)号：US20200304348A1
公开(公告)日：2020-09-24
申请号：US16841385
申请日：2020-04-06
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
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公开(公告)号：US10708036B2
公开(公告)日：2020-07-07
申请号：US15907200
申请日：2018-02-27
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe
Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
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109.发明授权公开(公告)号：US10659024B2
公开(公告)日：2020-05-19
申请号：US16658792
申请日：2019-10-21
Applicant: Rambus Inc.
Inventor： Brian Hing-Kit Tsang , Jared L. Zerbe
IPC: G11C11/16 , H03K5/133 , H03K3/03 , G11C7/22 , G11C7/10 , G06F13/16 , H03L7/00 , G11C8/18 , H03K7/06 , H01L43/08 , H03K5/00 , G11C11/15
Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
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公开(公告)号：US10652052B2
公开(公告)日：2020-05-12
申请号：US16432283
申请日：2019-06-05
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
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