公开(公告)号：US08405076B2

公开(公告)日：2013-03-26

申请号：US12920154

申请日：2010-02-03

申请人： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

发明人： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

IPC分类号： H01L29/12

CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675

摘要： A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2). [Mathematical Expression 13] MOx+(y−x)O2−MOy+2(y−x)e−  (Formula 13)

摘要翻译： 非易失性存储元件（100）包括可变电阻层（107），其包括第一金属氧化物MOx和第二金属氧化物MOy，以及与第一金属氧化物，第二金属氧化物，氧离子和 电子为2eV以下。 化学反应由式13表示，其中MOx和MOy的组合（MOx，MOy）选自（Cr 2 O 3，CrO 3），（Co 3 O 4，Co 2 O 3），（Mn 3 O 4，Mn 2 O 3），（VO 2，V 2 O 5） ），（Ce 2 O 3，CeO 2），（W3O 8，WO 3），（Cu 2 O，CuO），（SnO，SnO 2），（NbO 2，Nb 2 O 5）和（Ti 2 O 3，TiO 2）。 [数学表达式13] MOx +（y-x）O2-MOy + 2（y-x）e-（式13）

公开(公告)号：US20120280199A1

公开(公告)日：2012-11-08

申请号：US13512178

申请日：2010-11-18

申请人： Takeshi Takagi

发明人： Takeshi Takagi

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

摘要： Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.

摘要翻译： 提供了实现稳定的电阻变化和小型化的非易失性存储元件及其制造方法。 非易失性存储元件包括：形成在衬底上的第一电极; 形成在包括所述第一电极并且具有到达所述第一电极的存储单元孔的所述基板的上方的层间绝缘层; 由存储单元孔形成的阻挡层，由与第一电极连接的半导体层或绝缘层构成; 形成在所述存储单元孔中并连接到所述阻挡层的第二电极; 形成在所述第二电极上并具有电阻值基于电信号而变化的堆叠结构的可变电阻层; 以及连接到所述可变电阻层并形成在所述层间绝缘层上以覆盖所述存储单元孔的第三电极。

公开(公告)号：US08227786B2

公开(公告)日：2012-07-24

申请号：US12967624

申请日：2010-12-14

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L47/00 ,  G11C11/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1691

摘要： A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

摘要翻译： 一种非易失性存储元件，包括：第一电极2; 形成在第一电极2上方的第二电极6; 形成在第一电极2和第二电极6之间的可变电阻膜4，通过施加在第一和第二电极2,6之间的电脉冲，可变电阻膜4的电阻值增加或减小; 以及设置在第一和第二电极2,6之间的层间绝缘膜3，其中层间绝缘膜3设置有从其表面延伸到第一电极2的开口; 可变电阻膜4形成在开口的内壁面上; 并且由可变电阻膜4限定的开口的内部区域填充有嵌入绝缘膜5。

公开(公告)号：US20120104351A1

公开(公告)日：2012-05-03

申请号：US13382321

申请日：2011-06-29

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： H01L45/00

CPC分类号： H01L27/2409 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633

摘要： A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.

摘要翻译： 层叠结构，其中包括第一导电层（13），半导体层（17）和第二导电层（18）和层间绝缘膜（16）的层叠体（21）与 基板，多个柱状电极（12），被布置成沿堆叠方向穿过堆叠结构，设置在柱状电极（12）和第一导电层（13）之间的可变电阻层（14）和 其具有根据电信号的应用可逆地改变的电阻值。 可变电阻层（14）通过氧化第一导电层（13）的一部分而形成。 在单次氧化过程中同时形成可变电阻层（14）和用于将半导体层（17）和第二导电层（18）与柱状电极（12）电分离的绝缘膜。

公开(公告)号：US20110299322A1

公开(公告)日：2011-12-08

申请号：US13201890

申请日：2011-02-01

申请人： Mitsuteru Iijima ,  Takeshi Takagi

发明人： Mitsuteru Iijima ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/146

摘要： A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high to low, each of the two metal oxide layers having a different degree of oxygen deficiency; and performing an erasing step by applying an erasing voltage pulse having a second polarity to the transition metal oxide so as to change the resistance state of the transition metal oxide from low to high, the second polarity being different from the first polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps, and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, where N is equal to or more than 1, te1>te2 is satisfied, where te1 represents a pulse width of the erasing voltage pulse for first to M-th erasing steps, and te2 represents a pulse width of the erasing voltage pulse for (M+1)-th and subsequent erasing steps, where M is equal to or more than 1, and the (N+1)-th writing step follows the M-th erasing step.

摘要翻译： 编程可变电阻元件的方法包括：通过将包含第一极性的写入电压脉冲施加到包含堆叠的两个金属氧化物层的过渡金属氧化物来进行写入步骤，以改变过渡金属氧化物的电阻状态 从高到低，两个金属氧化物层中的每一个具有不同程度的氧气缺乏; 以及通过向所述过渡金属氧化物施加具有第二极性的擦除电压脉冲以便将所述过渡金属氧化物的电阻状态从低变为高而进行擦除步骤，所述第二极性与所述第一极性不同，其中| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤的写入电压脉冲的电压值，其中N是 等于或大于1，则te1> te2被满足，其中te1表示用于第一至第M擦除步骤的擦除电压脉冲的脉冲宽度，te2表示（M + 1）个擦除电压脉冲的脉冲宽度， 其中M等于或大于1，并且第（N + 1）个写入步骤在第M擦除步骤之后。

公开(公告)号：US20110140828A1

公开(公告)日：2011-06-16

申请号：US12967624

申请日：2010-12-14

申请人： Takumi MIKAWA ,  Takeshi Takagi

发明人： Takumi MIKAWA ,  Takeshi Takagi

IPC分类号： H01C7/18

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1691

摘要： A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

摘要翻译： 一种非易失性存储元件，包括：第一电极2; 形成在第一电极2上方的第二电极6; 形成在第一电极2和第二电极6之间的可变电阻膜4，通过施加在第一和第二电极2,6之间的电脉冲，可变电阻膜4的电阻值增加或减小; 以及设置在第一和第二电极2,6之间的层间绝缘膜3，其中层间绝缘膜3设置有从其表面延伸到第一电极2的开口; 可变电阻膜4形成在开口的内壁面上; 并且由可变电阻膜4限定的开口的内部区域填充有嵌入绝缘膜5。

公开(公告)号：US20100264392A1

公开(公告)日：2010-10-21

申请号：US12742841

申请日：2008-11-14

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.

摘要翻译： 非易失性存储器件包括分别形成在第一布线（11）与第二布线（14）交叉的横截面处的通孔（12），以及各自包括电流控制层（13b）的电流控制元件（13），第一电极层 （13a）和第二电极层（13c），使得电流控制层（13b）夹在第一电极层（13a）和第二电极层（13c）之间，其中电阻可变元件（15）设置在其内 通孔（12）分别设置成覆盖通孔（12），电流控制层（13b）被设置成覆盖第一电极层（13a）， 第二电极层（13c）设置在电流控制层（13b）上，第二导线的导线层（14a）设置在第二电极层（13c）上，第二导线（14）各自包括电流 控制层（13b），第二电极层（13c）和第二wi的导线层（14a） 回覆。

公开(公告)号：US20100193760A1

公开(公告)日：2010-08-05

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： H01L45/00 ,  H01L27/04 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US20100090193A1

公开(公告)日：2010-04-15

申请号：US12445380

申请日：2007-10-12

申请人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

发明人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

摘要翻译： 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29）以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US07679744B2

公开(公告)日：2010-03-16

申请号：US11987714

申请日：2007-12-04

申请人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

发明人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

IPC分类号： G01J4/00

CPC分类号： G01J4/00

摘要： The invention provides a Stokes parameter measurement device and Stokes parameter measurement method that enable high-precision measurement. The Stokes parameter measurement device comprises a polarization splitting device which comprises an optical element formed of a birefringent crystal material and which, by means of the optical element, splits signal light to be measured into a plurality of polarized light beams and adjusts the polarization state of one or more among the plurality of polarized light beams, and a light-receiving portion for performing photoelectric conversion of an optical component of the signal light split by and emitted from the polarization splitting device.

摘要翻译： 本发明提供了能够进行高精度测量的斯托克斯参数测量装置和斯托克斯参数测量方法。 斯托克斯参数测量装置包括偏振分离装置，其包括由双折射晶体材料形成的光学元件，并且通过光学元件将待测量的信号光分解为多个偏振光束并调节偏振态 多个偏振光束中的一个或多个，以及用于对由偏振分离装置分离和发射的信号光的光学分量执行光电转换的光接收部分。