公开(公告)号：US11672126B2

公开(公告)日：2023-06-06

申请号：US17137768

申请日：2020-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B51/20 ,  H01L27/11597 ,  H01L27/11587 ,  H10B51/10

CPC classification number: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

公开(公告)号：US11664278B2

公开(公告)日：2023-05-30

申请号：US16935830

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823431 ,  H01L21/76816 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US11631749B2

公开(公告)日：2023-04-18

申请号：US17681588

申请日：2022-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/768

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a side of the dummy gate. The dummy gate is replaced with a gate structure, such that that first gate spacer is on a side of the gate structure. The gate structure is etched back. After etching back the gate structure, a top portion of the first gate spacer is removed. A second gate spacer is formed over a remaining portion of the first gate spacer. After forming the second gate spacer, a dielectric cap is formed over the gate structure.

公开(公告)号：US20230008614A1

公开(公告)日：2023-01-12

申请号：US17815761

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chu-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US11532550B2

公开(公告)日：2022-12-20

申请号：US16875809

申请日：2020-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/288 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.

公开(公告)号：US11532343B2

公开(公告)日：2022-12-20

申请号：US17064279

申请日：2020-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11582

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

公开(公告)号：US11521858B2

公开(公告)日：2022-12-06

申请号：US17174990

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

公开(公告)号：US20220367379A1

公开(公告)日：2022-11-17

申请号：US17871272

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

公开(公告)号：US20220367284A1

公开(公告)日：2022-11-17

申请号：US17873903

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.

公开(公告)号：US20220359571A1

公开(公告)日：2022-11-10

申请号：US17869086

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/12 ,  H01L21/84

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.