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公开(公告)号:US20210335726A1
公开(公告)日:2021-10-28
申请号:US16931992
申请日:2020-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu , Chung-Shi Liu
IPC: H01L23/00 , H01L25/065 , H01L23/538 , H01L21/48 , H01L25/00
Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.
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公开(公告)号:US20210225764A1
公开(公告)日:2021-07-22
申请号:US17222225
申请日:2021-04-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu , Chien-Hsun Chen
IPC: H01L23/522 , H01L25/16 , H01L23/528 , H01L23/00 , H01L21/768 , H01L23/48
Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.
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公开(公告)号:US20210202396A1
公开(公告)日:2021-07-01
申请号:US16932364
申请日:2020-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu
IPC: H01L23/538 , H01L23/00 , H01L23/498 , H01L25/18 , H01L25/00 , H01L21/48
Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.
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公开(公告)号:US20210082827A1
公开(公告)日:2021-03-18
申请号:US17107181
申请日:2020-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu , Chung-Shi Liu , Chien-Hsun Lee
IPC: H01L23/538 , H01L23/31 , H01L25/18 , H01L21/56 , H01L23/00
Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
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公开(公告)号:US09460977B2
公开(公告)日:2016-10-04
申请号:US14968066
申请日:2015-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu
IPC: H01L23/48 , H01L23/31 , H01L25/065 , H01L23/00 , H01L25/10 , H01L23/13 , H01L21/683 , H01L23/498 , H01L21/56 , H01L25/00
CPC classification number: H01L23/3121 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2221/68372 , H01L2221/68381 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad.
Abstract translation: 插入器包括芯介电材料,穿透芯介质材料的导电管和导电管下面的金属垫。 金属焊盘包括与由导电管包围的区域重叠的中心部分和与导电管接触的外部部分。 电介质层位于芯介质材料和金属垫的下面。 通孔在电介质层中,其中通孔与金属焊盘的中心部分物理接触。
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公开(公告)号:US12243829B2
公开(公告)日:2025-03-04
申请号:US17808889
申请日:2022-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/16 , H01L23/31
Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.
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公开(公告)号:US20250062173A1
公开(公告)日:2025-02-20
申请号:US18934747
申请日:2024-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua Yu , Chien-Hsun Lee , Jiun Yi Wu
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498
Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.
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公开(公告)号:US12211779B2
公开(公告)日:2025-01-28
申请号:US17233081
申请日:2021-04-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu
IPC: H01L23/498 , H01L23/00
Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.
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公开(公告)号:US12205879B2
公开(公告)日:2025-01-21
申请号:US18362401
申请日:2023-07-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jiun Yi Wu , Chen-Hua Yu
IPC: H01L23/495 , H01L21/48 , H01L23/498
Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.
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公开(公告)号:US20240427081A1
公开(公告)日:2024-12-26
申请号:US18401851
申请日:2024-01-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Ning Weng , Yu-Ming Chou , Shih Wei Liang , Nien-Fang Wu , Jiun Yi Wu , Chen-Hua Yu
Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.
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