Semiconductor Package and Method
    101.
    发明申请

    公开(公告)号:US20210335726A1

    公开(公告)日:2021-10-28

    申请号:US16931992

    申请日:2020-07-17

    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

    Semiconductor Device and Method of Manufacturing

    公开(公告)号:US20210202396A1

    公开(公告)日:2021-07-01

    申请号:US16932364

    申请日:2020-07-17

    Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.

    Semiconductor Device and Method of Manufacture

    公开(公告)号:US20210082827A1

    公开(公告)日:2021-03-18

    申请号:US17107181

    申请日:2020-11-30

    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

    Semiconductor package having multiple substrates

    公开(公告)号:US12211779B2

    公开(公告)日:2025-01-28

    申请号:US17233081

    申请日:2021-04-16

    Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

    Symmetrical substrate for semiconductor packaging

    公开(公告)号:US12205879B2

    公开(公告)日:2025-01-21

    申请号:US18362401

    申请日:2023-07-31

    Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

    OPTICAL DEVICE AND METHOD OF MANUFACTURE

    公开(公告)号:US20240427081A1

    公开(公告)日:2024-12-26

    申请号:US18401851

    申请日:2024-01-02

    Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.

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