Suppressing digital-to-analog converter (DAC) error
    101.
    发明授权
    Suppressing digital-to-analog converter (DAC) error 有权
    抑制数模转换器(DAC)错误

    公开(公告)号:US07030792B2

    公开(公告)日:2006-04-18

    申请号:US11237250

    申请日:2005-09-28

    申请人: Feng Chen

    发明人: Feng Chen

    CPC分类号: H03M1/0663 H03M3/464

    摘要: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.

    摘要翻译: 数模转换器(DAC)误差抑制装置抑制由作为调制器(图6)的一部分的DAC(640和/或645)中包含的不匹配元件引起的DAC误差。 低通平均(LPA)索引解码器650控制移位装置635以移位从调制器输出Y导出的数字字T 2,使得DAC误差分布构成低通廓线(图5)。 因此,在较高频率(接近采样速率的一半)时DAC误差被抑制,从而提供改善的无杂散动态范围(SFDR)。 LPA索引解码器650使移位装置635在每个时钟周期仅使用单个指针来移位数字字T 2。

    Adaptive termination for optimum signal detection
    102.
    发明申请
    Adaptive termination for optimum signal detection 有权
    用于最佳信号检测的自适应终端

    公开(公告)号:US20050285621A1

    公开(公告)日:2005-12-29

    申请号:US10879513

    申请日:2004-06-29

    IPC分类号: H03K19/003 H04L25/02

    CPC分类号: H04L25/0278 H04L25/0292

    摘要: An integrated circuit includes a number of terminals to transfer signals. Each of the terminals has an adjustable termination impedance. The integrated circuit also includes a control circuit coupled to the terminals to adjust the value of the termination impedance of each of the terminals to improve signal detection at the terminals.

    摘要翻译: 集成电路包括用于传送信号的多个端子。 每个终端具有可调节的终端阻抗。 集成电路还包括耦合到端子的控制电路,以调整每个端子的端接阻抗的值,以改善端子处的信号检测。

    Method and structure for improving the linearity of MOS switches
    103.
    发明授权
    Method and structure for improving the linearity of MOS switches 有权
    提高MOS开关线性度的方法和结构

    公开(公告)号:US06897701B2

    公开(公告)日:2005-05-24

    申请号:US10436769

    申请日:2003-05-13

    IPC分类号: G05F3/26 H03K17/06 H03L5/00

    CPC分类号: H03K17/063 G05F3/262

    摘要: A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

    摘要翻译: 提供了一种用于线性化MOS开关导通电阻和非线性结电容的技术。 该技术通过使用具有适当DC偏移的具有基本上单位增益的缓冲器来线性化采样开关,以驱动MOS阱的隔离体端子以改善无杂散动态范围(SFDR)。 以这种方式,诸如非线性体效应(V SUB)和非线性结电容(C SUB)的二阶效应 (V SB SB))可以基本上除去。

    RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER
    104.
    发明申请
    RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER 有权
    可重构模拟数字转换器

    公开(公告)号:US20050057384A1

    公开(公告)日:2005-03-17

    申请号:US10661861

    申请日:2003-09-12

    摘要: Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

    摘要翻译: 配置模数转换器包括在模拟 - 数字转换器处接收控制信号和输入模拟信号,其中控制信号具有第一状态或第二状态。 第一状态与第一配置相关联,并且第二状态与第二配置相关联。 如果控制信号具有第一状态,则在第一配置中配置模数转换器,并且根据流水线转换产生包括第一数字信号的数字信号。 如果控制信号具有第二状态,则在第二配置中配置模数转换器,并且根据多级Σ-Δ调制转换产生包括第二数字信号的数字信号。 数字信号被处理以产生数字输出。

    Naphthalene derivatives as termite repellents and toxicants
    105.
    发明申请
    Naphthalene derivatives as termite repellents and toxicants 有权
    萘衍生物作为白蚁驱避剂和有毒物质

    公开(公告)号:US20050037045A1

    公开(公告)日:2005-02-17

    申请号:US10641315

    申请日:2003-08-14

    摘要: Several derivatives of naphthalene, including 1′-acetonaphthone, 2′-acetpnaphthone, 1-methoxynaphthalene, and 2-methoxynaphthalene, were discovered to be effective toxicants and repellents of termites, and resulted in significant reduction in termite feeding activity. For example, 2′-acetonaphthone was found to be an effective repellent and feeding deterrent of termites. Termites exposed to concentrations as low as 8 mg/kg sand exhibited a significant reduction in tunneling and feeding activity. Moreover, some of the dead termites had symptoms indicative of a failure to molt. At concentrations ≧20 μg/cm2, 2′-acetonaphthone was a strong repellent. Interestingly, at 160-fold lower concentration (0.125 μg/cm2), 2′-acetonaphthone stimulated termite feeding activity. As a sand barrier, 2′-acetonaphthone significantly inhibited tunneling and feeding activity in concentrations from 8.33 to 35.0 mg/kg. Molting problems were also identified in termites exposed to 2′-acetonaphthone.

    摘要翻译: 发现了萘的几种衍生物,包括1'-乙酰萘酮,2'-乙酸萘,1-甲氧基萘和2-甲氧基萘,是白蚁的有效毒素和驱避剂,导致白蚁进食活动显着降低。 例如,发现2'-乙酰萘酮是有效的驱避剂和抑制白蚁的威慑。 暴露于浓度低至8 mg / kg沙粒的白蚁显示隧道和进食活动的显着减少。 此外,一些死亡的白蚁有表现为蜕皮失败的症状。 当浓度> 20mug / cm 2时,2'-乙酰萘酮是强驱虫剂。 有趣的是,在浓度低于160倍(0.125马克/厘米2)的情况下,2'-乙酰萘酮刺激了白蚁进食活动。 作为沙屏障,2'-乙酰萘酮显着抑制了浓度为8.33〜35.0mg / kg的隧道和摄食活性。 在暴露于2'-乙酰四氢萘酮的白蚁中也发现了溶解问题。

    Apparatus and method for address calculation
    107.
    发明授权
    Apparatus and method for address calculation 有权
    用于地址计算的装置和方法

    公开(公告)号:US06735682B2

    公开(公告)日:2004-05-11

    申请号:US10112254

    申请日:2002-03-28

    IPC分类号: G06F1200

    CPC分类号: G06F9/3555

    摘要: A dual-cycle address generation unit is described to generate linear addresses. The dual-cycle address generation unit includes a first adder to add a product of an index and a scaling factor to an offset and a segment base during a first clock cycle and a second adder to add output of the first adder with a base during a second clock cycle.

    摘要翻译: 描述了一个双周期地址生成单元来生成线性地址。 双周期地址生成单元包括第一加法器,用于在第一时钟周期期间将索引和缩放因子的乘积加到偏移量和段基数,以及第二加法器,以在第一时钟周期期间将第一加法器的输出加到基极 第二个时钟周期。

    Pre STI-CMP planarization scheme
    108.
    发明授权
    Pre STI-CMP planarization scheme 有权
    预STI-CMP平坦化方案

    公开(公告)号:US06664190B2

    公开(公告)日:2003-12-16

    申请号:US09951916

    申请日:2001-09-14

    IPC分类号: H01L21311

    CPC分类号: H01L21/76229 H01L21/31053

    摘要: A new method of forming shallow trench isolations using a reverse mask process is described. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches is etched through the etch stop layer and the polish stop layer into the substrate whereby narrow active areas and wide active areas of the substrate are left between the isolation trenches. An oxide layer is deposited over the etch stop layer and within the isolation trenches. The oxide layer is covered with a mask in the narrow active areas and in the isolation trenches and etched away in the wide active areas stopping at the etch stop layer. Thereafter, the mask is removed and the etch stop layer is polished away to the polish stop layer whereby the oxide layer in the isolation trenches is planarized.

    摘要翻译: 描述了使用反掩模工艺形成浅沟槽隔离的新方法。 抛光停止层沉积在基底的表面上。 沉积在抛光停止层上的蚀刻停止层。 通过蚀刻停止层和抛光停止层将多个隔离沟槽蚀刻到衬底中,由此衬底的有源区域和宽的有源区域留在隔离沟槽之间。 氧化物层沉积在蚀刻停止层上方和隔离沟槽内。 在狭窄的有源区域和隔离沟槽中用掩模覆盖氧化物层,并在停止在蚀刻停止层处的宽有效区域中被蚀刻掉。 此后,去除掩模,并将蚀刻停止层抛光到抛光停止层,由此隔离沟槽中的氧化物层被平坦化。

    Method for detecting a dotting sequence for manchester encoded data in a deep fading environment
    109.
    发明授权
    Method for detecting a dotting sequence for manchester encoded data in a deep fading environment 有权
    用于在深度衰落环境中检测曼彻斯特编码数据的点序列的方法

    公开(公告)号:US06597752B1

    公开(公告)日:2003-07-22

    申请号:US09256573

    申请日:1999-02-24

    IPC分类号: H04L700

    CPC分类号: H04L7/046 H04L25/4904

    摘要: A method for a cellular telephone receiver to detect the presence of a dotting sequence for a Manchester encoded cellular signal in a deep fading environment, wherein the presence of a single edge transition during the mask pulse for a predetermined number of consecutive clock cycles and the absence of any transition edges outside of the mask pulse for the predetermined number of consecutive clock cycles, indicate the presence of a dotting sequence and that the cellular receiver locked to a masked edge, thereby preventing the receiver from receiving the signal. In response, the receiver will shift the phase of its clock by 180 degrees so that it can lock to an unmasked edge of the cellular signal and thereby receive the signal. By contrast, the absence of any transition edges or the presence of more than one transition edge during the mask pulse indicates that the receiver is not receiving the cellular signal because of deep fading and not because it locked to a masked edge of the signal during the dotting sequence. In response, the receiver will not shift the phase of its clock, but will instead remain locked to an unmasked edge so that it can receive the cellular signal once the deep fading ceases.

    摘要翻译: 一种用于蜂窝电话接收机检测在深衰落环境中曼彻斯特编码的蜂窝信号的点号序列的存在的方法,其中在掩模脉冲期间在预定数量的连续时钟周期内存在单个边沿跃迁以及不存在 在预定数量的连续时钟周期之外的掩模脉冲之外的任何过渡边缘的指示指示出点阵序列,并且蜂窝接收机锁定到被屏蔽的边缘,从而防止接收机接收信号。 作为响应,接收器将其时钟的相位移动180度,使得其可以锁定到蜂窝信号的未屏蔽边缘,从而接收信号。 相比之下,在掩模脉冲期间没有任何过渡边缘或多于一个过渡边缘的存在表明接收机由于深度衰落而没有接收蜂窝信号,而不是因为它在信号的屏蔽边缘被锁定 点序列 作为响应,接收机不会移动其时钟的相位,而是保持锁定到未屏蔽的边缘,使得一旦深度衰落停止,它可以接收蜂窝信号。

    Polishing apparatus and method for forming an integrated circuit
    110.
    发明授权
    Polishing apparatus and method for forming an integrated circuit 失效
    抛光装置和形成集成电路的方法

    公开(公告)号:US06443809B1

    公开(公告)日:2002-09-03

    申请号:US09440722

    申请日:1999-11-16

    IPC分类号: B24B722

    CPC分类号: B24B37/26 B24B37/042 B24D7/14

    摘要: In one embodiment, a semiconductor substrate (38) is uniformly polished using a polishing pad (16) that has a first polishing region (26), a second polishing region (28), and a third polishing region (30). The semiconductor substrate (38) is aligned to the polishing pad (16), such that the center of the semiconductor substrate (38) overlies the second polishing region (28), and the edge of the semiconductor substrate overlies the first polishing region (26) and the third polishing region (30). During polishing, the semiconductor substrate (38) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (38). This allows the semiconductor substrate (38) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate (38) are not over polished.

    摘要翻译: 在一个实施例中,使用具有第一抛光区域(26),第二抛光区域(28)和第三抛光区域(30)的抛光垫(16)均匀地抛光半导体衬底(38)。 半导体衬底(38)与抛光垫(16)对准,使得半导体衬底(38)的中心覆盖在第二抛光区域(28)上,并且半导体衬底的边缘覆盖在第一抛光区域(26) )和第三抛光区域(30)。 在抛光期间,半导体衬底(38)不在抛光垫的表面上径向摆动,结果在半导体衬底(38)上实现了更均匀的抛光速率。 这允许半导体衬底(38)从中心到边缘被均匀抛光,并且由于位于半导体衬底(38)上的裸芯未被抛光,所以提高了裸片的产量。