公开(公告)号：US20050057384A1

公开(公告)日：2005-03-17

申请号：US10661861

申请日：2003-09-12

申请人： Feng Chen ,  Ranjit Gharpurey

发明人： Feng Chen ,  Ranjit Gharpurey

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/16 ,  H03M3/00 ,  H03M3/04

CPC分类号： H03M1/005 ,  H03M1/167 ,  H03M3/398 ,  H03M3/416

摘要： Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

摘要翻译： 配置模数转换器包括在模拟 - 数字转换器处接收控制信号和输入模拟信号，其中控制信号具有第一状态或第二状态。 第一状态与第一配置相关联，并且第二状态与第二配置相关联。 如果控制信号具有第一状态，则在第一配置中配置模数转换器，并且根据流水线转换产生包括第一数字信号的数字信号。 如果控制信号具有第二状态，则在第二配置中配置模数转换器，并且根据多级Σ-Δ调制转换产生包括第二数字信号的数字信号。 数字信号被处理以产生数字输出。

公开(公告)号：US06914549B2

公开(公告)日：2005-07-05

申请号：US10661861

申请日：2003-09-12

申请人： Feng Chen ,  Ranjit Gharpurey

发明人： Feng Chen ,  Ranjit Gharpurey

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/16 ,  H03M3/00 ,  H03M3/04

CPC分类号： H03M1/005 ,  H03M1/167 ,  H03M3/398 ,  H03M3/416

摘要： Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

摘要翻译： 配置模数转换器包括在模拟 - 数字转换器处接收控制信号和输入模拟信号，其中控制信号具有第一状态或第二状态。 第一状态与第一配置相关联，并且第二状态与第二配置相关联。 如果控制信号具有第一状态，则在第一配置中配置模数转换器，并且根据流水线转换产生包括第一数字信号的数字信号。 如果控制信号具有第二状态，则在第二配置中配置模数转换器，并且根据多级Σ-Δ调制转换产生包括第二数字信号的数字信号。 数字信号被处理以产生数字输出。

公开(公告)号：US07187917B2

公开(公告)日：2007-03-06

申请号：US10811584

申请日：2004-03-29

申请人： Heng-Chih Lin ,  Ranjit Gharpurey

发明人： Heng-Chih Lin ,  Ranjit Gharpurey

IPC分类号： H04B1/26

CPC分类号： H03B27/00 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0033 ,  H03D2200/0086

摘要： A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 includes at least one “circuit portion” (FIG. 2A) configured to receive first and second orthogonal oscillator input signals (two of I, I−, Q, Q−) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (φM) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixer 230 is configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

摘要翻译： 电路提供根据输入信号231调制的减少的谐波含量输出信号OUTA和/或OUTB。 电路具有振荡电路210和谐波抑制混频器（HRM）230。 振荡器电路210包括至少一个“电路部分”（图2A），其被配置为接收具有相应的第一和第二相位的第一和第二正交振荡器输入信号（I，I，I，Q-中的两个），并且 提供任意大量的振荡器输出信号（phiM），其具有在第一和第二相之间插值的各自相互不同的相位。 谐波抑制混频器230被配置为使用输入信号来调制振荡器输出信号的组合，振荡器输出信号被分别加权，以便提供构成还原谐波内容输出信号的仿真正弦信号。

公开(公告)号：US07187909B2

公开(公告)日：2007-03-06

申请号：US10811704

申请日：2004-03-29

申请人： Heng-Chih Lin ,  Ranjit Gharpurey ,  Paul A. Fontaine

发明人： Heng-Chih Lin ,  Ranjit Gharpurey ,  Paul A. Fontaine

IPC分类号： H04B1/02 ,  H04B17/00

CPC分类号： H03F3/24 ,  H03F3/345 ,  H04B1/04

摘要： A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

摘要翻译： 当前域发射机被配置为接收输入信号并提供发射信号。 发射机具有多个元件，可操作地布置在输入信号和发射信号之间，并被配置为用相应的电流表示输入信号，其各自的电流幅度大致与输入信号成比例。 元件可以包括电流转向数模转换器（DAC），电流模式滤波器（例如LPF），电流模式混频器和/或电流模式放大器。

公开(公告)号：US20050212599A1

公开(公告)日：2005-09-29

申请号：US10806962

申请日：2004-03-23

申请人： Heng-Chih Lin ,  Ranjit Gharpurey

发明人： Heng-Chih Lin ,  Ranjit Gharpurey

IPC分类号： H03F3/45

CPC分类号： H03F3/45659 ,  H03F2200/453

摘要： The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

摘要翻译： 具有自适应放大器输出共模电压调节的电路包括：差分前置放大器; 重新产生的比较器，其具有耦合到前置放大器的差分输出的差分输入; 以及耦合到前置放大器的共模节点的复制比较器，用于调整前置放大器的共模。 复制比较器提供了一个跳变点参考，用于设置前置放大器的输出共模。 这将前置放大器的输出共模设置为重新产生的比较器的最敏感区域。

公开(公告)号：US07440491B2

公开(公告)日：2008-10-21

申请号：US10759480

申请日：2004-01-16

申请人： Jaiganesh Balakrishnan ,  Anuj Batra ,  Anand G. Dabak ,  Abdellatif Bellaouar ,  Paul H. Fontaine ,  Michel Frechette ,  Ranjit Gharpurey ,  Heng-Chih Lin

发明人： Jaiganesh Balakrishnan ,  Anuj Batra ,  Anand G. Dabak ,  Abdellatif Bellaouar ,  Paul H. Fontaine ,  Michel Frechette ,  Ranjit Gharpurey ,  Heng-Chih Lin

IPC分类号： H04B1/00

CPC分类号： H04B1/719 ,  H04B1/71635 ,  H04B1/71637

摘要： System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

摘要翻译： 用于在存在干扰源的情况下在扩展工作范围内提供高数据速率的超宽带通信系统。 优选实施例包括利用UWB频率范围的一部分来帮助在存在干扰源的情况下提供良好性能的超宽带（UWB）设备。 此外，由于仅使用UWB频率范围的一部分，所以多个设备可以通过使用UWB频率范围的不同部分同时发送和接收。

公开(公告)号：US06975170B2

公开(公告)日：2005-12-13

申请号：US10806962

申请日：2004-03-23

申请人： Heng-Chih Lin ,  Ranjit Gharpurey

发明人： Heng-Chih Lin ,  Ranjit Gharpurey

IPC分类号： H03F3/45

CPC分类号： H03F3/45659 ,  H03F2200/453

摘要： The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

公开(公告)号：US06456223B1

公开(公告)日：2002-09-24

申请号：US09715228

申请日：2000-11-17

申请人： Paul C. Yu ,  Shereef Shehata ,  Ranjit Gharpurey

发明人： Paul C. Yu ,  Shereef Shehata ,  Ranjit Gharpurey

IPC分类号： H03M138

CPC分类号： H03M1/08 ,  H03M1/0673 ,  H03M1/168

摘要： In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model. Finally, the cancellation factor is subtracted from an ADC output to substantially reduce and/or effectively cancel the mismatch noise.

摘要翻译： 在具有模拟输入信号和数字输出信号并且具有多个流水线级的流水线模数转换器（ADC）中，每个这样的级具有模拟输入，包括残余电压的模拟输出和数字 输出，所述级包括具有多个电容器的数模转换器子级，其根据预定的过程用于采样保持功能并进行混洗;一种用于在电容器中减少由混洗产生的噪声的方法 不匹配。 该方法包括以下步骤。 首先，提供从混洗产生的噪声的估计模型。 估计模型包括与电容器不匹配相对应的因素。 基于对该阶段的输出参数的监视来估计阶段中的电容器之间的不匹配。 通过将不匹配估计应用于估计模型来生成消除因子。 最后，从ADC输出中减去消除因子，以显着减少和/或有效地消除失配噪声。

公开(公告)号：US06400224B2

公开(公告)日：2002-06-04

申请号：US09770335

申请日：2001-01-26

申请人： Ranjit Gharpurey

发明人： Ranjit Gharpurey

IPC分类号： H03F345

CPC分类号： H03F3/193 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/372 ,  H03F2203/45704

摘要： A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) And provides image rejection without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.

摘要翻译： 两级低噪声放大器（10）包括第一级（12）和第二级（14）。 第一级（12）接收输入信号（VIN），对输入信号（VIN）执行单差分转换，并从其产生输入差分信号（VA和VB）。 可以将输入差分信号（VA和VB）的偏置电平调整到第二级（14）的最佳偏置点。 第一级（12）向第二级（14）提供输入差分信号（VA和VB），并且在放大器增益没有任何损耗的情况下提供镜像抑制。 第二级（14）对输入差分信号（VA和VB）进行图像抑制，并从其产生输出差分信号（V +和V-）。 第一级（12）和级（14）包括调整放大器（10）的中心工作频率的调谐电路。 第一级（12）和第二级（14）接收来自控制总线（16）的控制信号，以调整中心工作频率。

公开(公告)号：US20130175262A1

公开(公告)日：2013-07-11

申请号：US13734398

申请日：2013-01-04

申请人： Ranjit Gharpurey ,  Jacob A. Abraham

发明人： Ranjit Gharpurey ,  Jacob A. Abraham

IPC分类号： H05B6/72

CPC分类号： H05B6/72 ,  H05B6/70

摘要： Techniques are disclosed relating to microwave ovens. In one embodiment, an apparatus is disclosed that includes a microwave heating unit. The microwave heating unit is configured to radiate microwaves into a cavity and includes an antenna array coupled to one or more amplifiers. The antenna array is configured to generate the radiated microwaves. In some embodiments, the microwave oven is configured to measure temperatures of a item within the cavity, and to steer a microwave beam produced by the antenna array based on the measured temperatures.

摘要翻译： 公开了涉及微波炉的技术。 在一个实施例中，公开了一种包括微波加热单元的装置。 微波加热单元被配置为将微波辐射到空腔中并且包括耦合到一个或多个放大器的天线阵列。 天线阵列被配置为产生辐射的微波。 在一些实施例中，微波炉被配置为测量空腔内的物品的温度，并且基于所测量的温度控制由天线阵列产生的微波束。