公开(公告)号：US07944730B2

公开(公告)日：2011-05-17

申请号：US12412546

申请日：2009-03-27

申请人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.

摘要翻译： 写入电阻式读出存储器单元的方法包括在电阻读出存储单元和半导体晶体管两端施加第一电压以将第一数据状态写入电阻读出存储单元。 第一电压在第一方向通过电阻读出存储单元形成第一持续时间的第一写入电流。 然后，该方法包括在电阻读出存储单元和晶体管两端施加第二电压以将第二数据状态写入电阻读出存储单元。 第二电压在第二方向通过电阻读出存储器单元形成第二持续时间的第二写入电流。 第二方向与第一方向相反，第一电压具有与第二电压不同的值，并且第一持续时间基本上与第二持续时间相同。

公开(公告)号：US20110080782A1

公开(公告)日：2011-04-07

申请号：US12967743

申请日：2010-12-14

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/15

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

公开(公告)号：US20110007588A1

公开(公告)日：2011-01-13

申请号：US12502194

申请日：2009-07-13

申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C15/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

公开(公告)号：US20110007549A1

公开(公告)日：2011-01-13

申请号：US12502210

申请日：2009-07-13

申请人： Xuguang Wan ,  Hai Li ,  Hongyue Liu

发明人： Xuguang Wan ,  Hai Li ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C11/16 ,  G11C7/18 ,  G11C11/1659 ,  G11C11/1673

摘要： A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.

摘要翻译： 电阻式感测存储装置包括第一半导体晶体管，其具有电连接到第一源极线的第一接触点和电连接到第一电阻性感测存储元件的第二接触点，以及第二半导体晶体管，其具有电连接到第二源极线 以及电连接到第二电阻读出存储元件的第二触点。 位线电连接到第一电阻读出存储器元件和第二电阻读出存储元件。

公开(公告)号：US07852665B2

公开(公告)日：2010-12-14

申请号：US12406356

申请日：2009-03-18

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2207/063

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.

摘要翻译： 本发明的各种实施例通常涉及用于感测诸如自旋扭矩传递随机存取存储器（STRAM）单元的存储器单元的编程状态的方法和装置。 将第一读取电流施加到存储器单元以产生第一电压。 随后将第二读取电流施加到存储器单元以产生第二电压，其中第二读取电流在幅度上与第一读取电流成比例。 在第一和第二电压之间进行比较以确定存储器单元的编程状态。

公开(公告)号：US20100110762A1

公开(公告)日：2010-05-06

申请号：US12412546

申请日：2009-03-27

申请人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.

摘要翻译： 写入电阻式读出存储器单元的方法包括在电阻读出存储单元和半导体晶体管两端施加第一电压以将第一数据状态写入电阻读出存储单元。 第一电压在第一方向通过电阻读出存储单元形成第一持续时间的第一写入电流。 然后，该方法包括在电阻读出存储单元和晶体管两端施加第二电压以将第二数据状态写入电阻读出存储单元。 第二电压在第二方向通过电阻读出存储器单元形成第二持续时间的第二写入电流。 第二方向与第一方向相反，第一电压具有与第二电压不同的值，并且第一持续时间基本上与第二持续时间相同。

公开(公告)号：US20100110761A1

公开(公告)日：2010-05-06

申请号：US12398256

申请日：2009-03-05

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C5/025 ,  G11C11/1653 ,  G11C11/1673

摘要： The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

摘要翻译： 本公开涉及将参考列或参考行选择性地放置在存储器阵列中的方法。 该方法包括测量存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值，并映射每个测量的可变电阻存储单元的位置，以形成多个可变电阻存储单元的电阻状态电阻值的映射 在内存阵列内。 然后，基于存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值的映射来选择列或行作为参考列或参考行，以最小化读取操作错误，以及形成可变电阻存储器 单元存储器阵列。

公开(公告)号：US08526252B2

公开(公告)日：2013-09-03

申请号：US12405932

申请日：2009-03-17

申请人： Hai Li ,  Yiran Chen ,  Alan Xuguang Wang ,  Haiwen Xi ,  Wenzhong Zhu ,  Andreas K. Roelofs

发明人： Hai Li ,  Yiran Chen ,  Alan Xuguang Wang ,  Haiwen Xi ,  Wenzhong Zhu ,  Andreas K. Roelofs

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C11/16 ,  G11C29/025 ,  G11C2029/5006

摘要： A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.

摘要翻译： 用于测试非易失性存储器单元阵列的方法和装置，例如自旋转矩传递随机存取存储器（STRAM）。 在一些实施例中，具有多个具有电阻感测元件和开关器件的单位单元的存储器单元阵列具有连接到多个单位单元的行解码器和列解码器。 测试电路通过具有静态电源电流的行和列解码器通过阵列发送非操作测试模式，以识别存储器单元阵列中的缺陷。

公开(公告)号：US08526215B2

公开(公告)日：2013-09-03

申请号：US13410783

申请日：2012-03-02

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C5/025 ,  G11C11/1653 ,  G11C11/1673

摘要： The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

摘要翻译： 本公开涉及将参考列或参考行选择性地放置在存储器阵列中的方法。 该方法包括测量存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值，并映射每个测量的可变电阻存储单元的位置，以形成多个可变电阻存储单元的电阻状态电阻值的映射 在内存阵列内。 然后，基于存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值的映射来选择列或行作为参考列或参考行，以最小化读取操作错误，以及形成可变电阻存储器 单元存储器阵列。

公开(公告)号：US08411495B2

公开(公告)日：2013-04-02

申请号：US13349052

申请日：2012-01-12

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

IPC分类号： G11C11/00

CPC分类号： G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006 ,  Y10S977/933

摘要： A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

摘要翻译： 描述了自旋转移力矩存储装置和自参考读取方案。 读取自旋传递转矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压，所述磁性隧道结数据单元具有第一电阻状态并存储 第一电压存储装置中的第一位线读取电压。 然后通过磁性隧道结数据单元施加低电阻状态的极化写入电流，形成低的第二电阻状态磁隧道结数据单元。 第二读取电流通过低的第二电阻状态磁隧道结数据单元施加以形成第二位线读取电压。 第二位线读取电压被存储在第二电压存储装置中。 该方法还包括将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。