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110 条记录 (耗时 0.036 秒)

    Semiconductor memory device
    102.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06614712B2

    公开(公告)日：2003-09-02

    申请号：US10329669

    申请日：2002-12-27

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Semiconductor memory device
    103.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06545924B2

    公开(公告)日：2003-04-08

    申请号：US09929357

    申请日：2001-08-15

    申请人： Waichiro Fujieda ,  Shinya Fujioka

    发明人： Waichiro Fujieda ,  Shinya Fujioka

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.

    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
    104.
    发明授权
    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
    半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作

    公开(公告)号：US06427197B1

    公开(公告)日：2002-07-30

    申请号：US09394891

    申请日：1999-09-13

    申请人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    发明人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/1039

    摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

    摘要翻译： 本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址 写命令 第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。 根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。 此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

    DRAM for storing data in pairs of cells
    105.
    发明授权
    DRAM for storing data in pairs of cells 有权
    用于将数据存储在单元格对中的DRAM

    公开(公告)号：US06344990B1

    公开(公告)日：2002-02-05

    申请号：US09652015

    申请日：2000-08-31

    申请人： Masato Matsumiya ,  Shinya Fujioka ,  Kimiaki Satoh ,  Toru Miyabo

    发明人： Masato Matsumiya ,  Shinya Fujioka ,  Kimiaki Satoh ,  Toru Miyabo

    IPC分类号： G11C506

    CPC分类号： G11C7/02 ,  G11C7/1042 ,  G11C7/18 ,  G11C11/406 ,  G11C11/4097 ,  G11C2211/4013

    摘要： A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.

    摘要翻译： 一种包括存储单元阵列的存储电路。 存储单元阵列具有连接到与包括第一和第三位线的第一位线对相关联的一对存储器单元的第一字线组，以及连接到与第二位相关联的一对存储器单元的第二字线组 包括第二和第四位线的线对。 第一和第二读出放大器组分别位于存储器阵列的每一侧上，并且分别连接到第一和第二位线对。 当驱动第一字线组的任何字线时，第一读出放大器组被激活以反相驱动第一字线组，并且第二读出放大器组保持在非活动状态以保持第二字线组 在预充电水平。

    Memory device with a plurality of common data buses
    106.
    发明授权
    Memory device with a plurality of common data buses 有权
    具有多个公共数据总线的存储器件

    公开(公告)号：US06333890B1

    公开(公告)日：2001-12-25

    申请号：US09695302

    申请日：2000-10-25

    申请人： Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

    发明人： Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

    IPC分类号： G11C800

    CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C8/12 ,  G11C2207/108

    摘要： According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.

    摘要翻译： 根据本发明的一个方面，具有多个存储体的存储器件通过使用多个公共数据总线执行存储体交织，该数据总线的数量少于存储体的数量。 本发明能够在抑制芯片面积的增加的同时更快地读取数据。 根据本发明，提供了一种具有多个存储单元的存储器件，每个存储单元包括多个存储器单元，以及与时钟信号同步地从存储器单元读取或写入数据，所述存储器件包括：感测 放大器设置在所述多个存储体中的每一个上，用于放大从所述存储器单元读取的数据; 由所述多个银行共享的多个公用数据总线，所述公共数据总线的数量小于所述存储体的数量; 以及切换电路，其设置在所述多个存储体中的每一个上，用于向所述多个公共数据总线馈送或接收每个存储体的数据; 其中通过所述切换电路连续选择所述多个公用数据总线来进行所述多个存储体的数据的读取或写入。

    Bit line reset circuit of memory
    107.
    发明授权
    Bit line reset circuit of memory 失效
    存储器的位线复位电路

    公开(公告)号：US6026034A

    公开(公告)日：2000-02-15

    申请号：US73928

    申请日：1998-05-07

    申请人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    发明人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/12

    摘要： Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.

    摘要翻译： 开关晶体管20,22,22P，21,23和23P以及用于晶体管20和21的控制电路的一部分构成存储单元侧的位线复位电路。 在从连接到位线BLC或* BLC的存储单元读取“H”时，两个位线都被设置在较高的复位电位Vii，而在读取“L”时，两个位线都以较低的复位电位复位 Vss。 在充分放大位线BL和* BL之间的电位差之前，转移门10和11被截止。 与位线复位的操作并行执行从存储单元中恢复读取的操作。

    Step-up circuit using two frequencies
    108.
    发明授权
    Step-up circuit using two frequencies 失效
    升压电路使用两个频率

    公开(公告)号：US6020781A

    公开(公告)日：2000-02-01

    申请号：US932604

    申请日：1997-09-17

    申请人： Shinya Fujioka

    发明人： Shinya Fujioka

    IPC分类号： H01L27/04 ,  G11C11/407 ,  H01L21/822 ,  H02M3/07 ,  H03K3/03 ,  H03K17/00 ,  H03K17/06 ,  G05F1/10 ,  H03K3/02

    CPC分类号： H02M1/36 ,  H02M3/07 ,  H03K17/063 ,  H03K2217/0036 ,  H03K3/03

    摘要： A step-up circuit includes a selection control circuit 50 for activating a start/stop signal STP by detecting an external power-supply voltage Vcc, which is stable at 3.3 V, to reach 2.0 V or more, a ring oscillator circuit 30 for generating and outputting a clock of a high frequency Fs when the start/stop signal STP is inactive, a ring oscillator circuit 10 for generating a clock of a low frequency fo, a selection circuit 40 for selecting the output of the oscillator 30 when the start/stop signal STP is inactive and for selecting the output of the oscillator 10 when the start/stop signal is active, and a charging pump circuit 20 driven by the clocks. High frequency Fs is initially used to quickly bring an output voltage up to a desired operating level and low frequency fo is used, in order to conserve power, to maintain the operating level once a predetermined level of the external power supply voltage Vcc has been reached in order to conserve power.

    摘要翻译： 升压电路包括：选择控制电路50，用于通过检测稳定在3.3V的外部电源电压Vcc达到2.0V以上来启动启动/停止信号STP;环形振荡器电路30，用于产生 并且当启动/停止信号STP不活动时，输出高频Fs的时钟;用于产生低频率fo的时钟的环形振荡器电路10;选择电路40，用于当起动/停止信号STP不起动时选择振荡器30的输出; 停止信号STP不活动，并且用于当启动/停止信号有效时选择振荡器10的输出，以及由时钟驱动的充电泵电路20。 最初使用高频率Fs来将输出电压快速地提高到期望的工作电平并且使用低频率fo以便节省电力，以便在达到外部电源电压Vcc的预定电平达到之后保持工作电平 以节省电力。

    Clock generator having DLL and semiconductor device having clock generator
    109.
    发明授权
    Clock generator having DLL and semiconductor device having clock generator 失效
    具有DLL和具有时钟发生器的半导体器件的时钟发生器

    公开(公告)号：US5969551A

    公开(公告)日：1999-10-19

    申请号：US961181

    申请日：1997-10-30

    申请人： Shinya Fujioka

    发明人： Shinya Fujioka

    IPC分类号： G11C11/407 ,  G06F1/10 ,  G06F1/12 ,  G06F13/42 ,  G11C11/401 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/15 ,  H03K19/0175 ,  H03L7/081 ,  H03L7/087

    CPC分类号： H03K5/1506 ,  H03L7/0812 ,  H03L7/087

    摘要： A clock generator including a DLL occupying a small area and a semiconductor device including the clock generator have been disclosed. In the clock generator for generating a plurality of clocks optimally adjusted in phase for a plurality of objects on the basis of a received clock, the DLL is structured hierarchically. A first DLL of a parent level is used in common and second DLLs of child levels are associated with input signals.

    摘要翻译： 已经公开了一种包括占用小区域的DLL的时钟发生器和包括时钟发生器的半导体器件。 在时钟发生器中，基于接收到的时钟生成针对多个对象进行最佳相位调整的多个时钟，该DLL被分层结构化。 父级别的第一个DLL用于常见的子级别的第二个DLL与输入信号相关联。

    High-speed clock-synchronous semiconductor integrated circuit and semiconductor integrated circuit system
    110.
    发明授权
    High-speed clock-synchronous semiconductor integrated circuit and semiconductor integrated circuit system 失效
    高速时钟同步半导体集成电路和半导体集成电路系统

    公开(公告)号：US5923198A

    公开(公告)日：1999-07-13

    申请号：US978373

    申请日：1997-11-25

    申请人： Shinya Fujioka

    发明人： Shinya Fujioka

    IPC分类号： G06F1/10 ,  G06F5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  H03K19/003 ,  H03K19/0175 ,  H03H11/26

    CPC分类号： G11C7/1078 ,  G06F5/06 ,  G11C7/1051 ,  G11C7/22 ,  H03K19/00323

    摘要： A semiconductor integrated circuit has a de-skew circuit for reducing a skew of an incoming signal from a specific circuit with respect to a synchronous clock signal. The de-skew circuit controls the phase of an outgoing signal to be transmitted from the semiconductor integrated circuit to the specific circuit in response to the skew of the input signal. This arrangement decreases not only a skew of incoming signals from the specific circuit but also a skew of outgoing signals to the specific circuit.

    摘要翻译： 半导体集成电路具有去偏斜电路，用于相对于同步时钟信号减小来自特定电路的输入信号的偏斜。 去偏斜电路响应于输入信号的偏斜来控制要从半导体集成电路发送到特定电路的输出信号的相位。 这种布置不仅降低了来自特定电路的输入信号的偏斜，而且还降低了到特定电路的输出信号的偏斜。