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101.发明授权公开(公告)号：US10593728B1
公开(公告)日：2020-03-17
申请号：US16215023
申请日：2018-12-10
发明人： Curtis Chun-I Hsieh , Wanbing Yi , Yi Jiang , Juan Boon Tan
摘要： Integrated circuits and methods for fabricating magnetic tunnel junction (MTJ) structures and integrated circuits are provided. An exemplary method for fabricating an integrated circuit including a magnetic tunnel junction (MTJ) structure includes forming magnetic tunnel junction (MTJ) layers over a substrate. Further, the method includes forming a conductive pillar over the MTJ layers, wherein the conductive pillar is formed with an uppermost surface, and wherein the uppermost surface is not planarized. Also, the method includes etching the MTJ layers to form a pillar structure from portions of the MTJ layers underlying the conductive pillar.
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102.发明授权公开(公告)号：US10559691B2
公开(公告)日：2020-02-11
申请号：US16195150
申请日：2018-11-19
IPC分类号： H01L29/78 , H01L27/112 , H01L23/525 , H01L29/66 , H01L21/84 , H01L27/12
摘要： Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
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公开(公告)号：US10553701B2
公开(公告)日：2020-02-04
申请号：US16228797
申请日：2018-12-21
IPC分类号： H01L29/66 , H01L21/265 , H01L29/10 , H01L29/167
摘要： A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.
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104.发明授权公开(公告)号：US10516096B2
公开(公告)日：2019-12-24
申请号：US15938712
申请日：2018-03-28
摘要： Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.
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公开(公告)号：US10510859B2
公开(公告)日：2019-12-17
申请号：US16393028
申请日：2019-04-24
IPC分类号： H01L23/535 , H01L29/49 , H01L29/51 , H01L29/78 , H01L23/522 , H01L29/66 , H01L21/28 , H01L21/02
摘要： A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.
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106.发明授权公开(公告)号：US10504768B1
公开(公告)日：2019-12-10
申请号：US16021893
申请日：2018-06-28
发明人： Ke Dong , Purakh R. Verma , Shiang Yang Ong , Namchil Mun
IPC分类号： H01L21/70 , H01L21/74 , H01L21/762 , H01L23/535 , H01L21/768
摘要： The present disclosure relates to semiconductor structures and, more particularly, to contact structures to deep trench isolation structures and methods of manufacture. The structure includes: a deep trench structure lined with insulator material on sidewalls thereof; conductive material filling the deep trench structure; a local oxide extending above the trench on exposed portions of the insulator material; an interlevel dielectric material on the local oxide and the conductive material filling the deep trench structure; and a contact in the interlevel dielectric material, extending to the conductive material and on a side of the local oxide.
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公开(公告)号：US10438909B2
公开(公告)日：2019-10-08
申请号：US15429198
申请日：2017-02-10
发明人： Fook Hong Lee , Juan Boon Tan , Ee Jan Khor
IPC分类号： H01L23/31 , H01L23/525 , H01L21/768 , H01L23/00 , G06F17/50 , G03F1/36 , H01L23/528 , H01L23/532
摘要： Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.
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108.发明授权公开(公告)号：US10424616B1
公开(公告)日：2019-09-24
申请号：US16013715
申请日：2018-06-20
发明人： Yongshun Sun , Eng Huat Toh
摘要： Integrated circuit devices including vertical Hall elements and lateral Hall elements and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit device includes a substrate including a lateral element region and a vertical element region. The integrated circuit device includes a well in the lateral element region and in the vertical element region of the substrate. Further, the integrated circuit device includes an insulating layer disposed over the substrate in the lateral element region, a semiconductor-over-insulator (SOI) semiconductor layer disposed over the insulating layer in the lateral element region, and lateral element conductive taps located in the semiconductor layer, wherein a lateral Hall element is defined in the lateral element region. Also, the integrated circuit device includes vertical element taps located in the well in the vertical element region, wherein a vertical Hall element is defined in the vertical element region.
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公开(公告)号：US10418274B2
公开(公告)日：2019-09-17
申请号：US15657894
申请日：2017-07-24
IPC分类号： H01L21/02 , H01L29/06 , H01L29/16 , H01L21/762
摘要： Methods of increasing the optical path length and bandwidth of a Ge-based photodiode while reducing the diode area and capacitance without compromising the optical responsivity and the resulting devices are provided. Embodiments include providing a Si substrate having a BOX layer over the Si substrate and a Si layer over the BOX layer; forming an oxide layer over the Si layer; forming a trench in the oxide layer, the trench having a center strip and a plurality of opposing fins; epitaxially growing Ge in the trench and above the oxide layer; and removing the oxide layer, a Ge center strip and a plurality of opposing fins remaining.
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公开(公告)号：US10411027B2
公开(公告)日：2019-09-10
申请号：US15787764
申请日：2017-10-19
发明人： Ming Zhu , Pinghui Li , Eng Huat Toh , Yiang Aun Nga , Danny Pak-Chum Shum
IPC分类号： H01L29/78 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/11568 , H01L29/423 , H01L27/11573
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
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