公开(公告)号：US08963053B2

公开(公告)日：2015-02-24

申请号：US13412306

申请日：2012-03-05

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: H05B1/02 ,  G11C29/50 ,  G11C7/06 ,  G11C29/14 ,  G11C7/08 ,  G11C7/22 ,  G11C29/12

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

公开(公告)号：US20130202031A1

公开(公告)日：2013-08-08

申请号：US13827210

申请日：2013-03-14

Applicant: STMICROELECTRONICS PVT. LTD. ,  STMICROELECTRONICS SRL

Inventor： Subarna TRIPATHI ,  Emiliano PICCINELLI

IPC: H04N7/26

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/124 ,  H04N19/146 ,  H04N19/149 ,  H04N19/152 ,  H04N19/162 ,  H04N19/169 ,  H04N19/177 ,  H04N19/40

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract translation: 独立于GOP的动态比特率控制器系统包括用于接收一个或多个输入参数的用户界面，比特率控制器和编码器。 比特率控制器调节输出比特流的比特率。 比特率控制器包括用于确定比特估计和量化参数的多个比特率模块，以及基于所接收的输入参数和帧速率来计算收敛周期的控制模块。 控制模块基于收敛周期选择比特率模块，并且编码器使用由比特率模块确定的量化参数来生成输出比特流。

公开(公告)号：US20130170306A1

公开(公告)日：2013-07-04

申请号：US13340670

申请日：2011-12-29

Applicant: Navneet GUPTA ,  Prashant DUBEY ,  ShaileshKumar PATHAK ,  Kaushik SAHA ,  Ashish KUMAR ,  R Sai KRISHNA

Inventor： Navneet GUPTA ,  Prashant DUBEY ,  ShaileshKumar PATHAK ,  Kaushik SAHA ,  Ashish KUMAR ,  R Sai KRISHNA

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/08 ,  G11C7/227

Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.

Abstract translation: 读出放大器的实施例包括检测电路和监视电路。 感测电路被配置为将对应于存储在存储单元中的数据的第一信号转换成对应于数据的第二信号，并且监视电路被配置为指示第二信号的可靠性。 监视电路例如可以调整其中设置存储单元的存储器的参数以增加读取精度，并且还可以允许识别和校正由于无效的第二信号引起的错误。

公开(公告)号：US20130120650A1

公开(公告)日：2013-05-16

申请号：US13296965

申请日：2011-11-15

Applicant: Ravi ANANTHAPURBACCHE

Inventor： Ravi ANANTHAPURBACCHE

IPC: H04N7/12

CPC classification number: H04N9/78

Abstract: A video decoder includes an adaptive comber to generate a combed video image, and the adaptive comber selectively combs using 2D combing, frame combing, and field combing.

Abstract translation: 一种视频解码器包括一个自适应精梳器，用于产生一个精梳视频图像，并且该自适应精梳机使用二维梳理，帧梳理和场梳理选择性梳理。

公开(公告)号：US20130120588A1

公开(公告)日：2013-05-16

申请号：US13298130

申请日：2011-11-16

Applicant: RajeshSidana OMPRAKASH ,  Ravi Ananthapurbacche ,  Peter Swartz ,  JeongWoo Lee ,  Greg Neal ,  Ramesh Dandapani

Inventor： RajeshSidana OMPRAKASH ,  Ravi Ananthapurbacche ,  Peter Swartz ,  JeongWoo Lee ,  Greg Neal ,  Ramesh Dandapani

IPC: H04N17/00

CPC classification number: G09G5/003 ,  G06K9/3233 ,  G09G5/14 ,  G09G2320/0686 ,  G09G2320/103 ,  H04N5/144

Abstract: A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map.

Abstract translation: 视频窗口检测器包括：区域特征确定器，用于为显示输出的至少一个区域生成至少一个特征值; 特征图生成器，用于根据所述显示输出的至少一个区域的所述至少一个特征值生成图像映射; 以及窗口检测器，用于根据图像映射检测至少一个视频窗口。

公开(公告)号：US08411518B2

公开(公告)日：2013-04-02

申请号：US12981031

申请日：2010-12-29

Applicant: Dhori Kedar Janardan ,  Rakesh Kumar Sinha ,  Sachin Gulyani

Inventor： Dhori Kedar Janardan ,  Rakesh Kumar Sinha ,  Sachin Gulyani

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.

Abstract translation: 存储电路包括被配置为可重写的存储单元。 写入使能电路被配置为使得能够根据写入信号经由一对位线将信号写入存储器单元。 电荷供给电路被配置为向所述一对位线中的至少一个提供电荷。 电荷供给控制器被配置为控制充电电路根据存储电路的温度和存储电路的电位差供给中的至少一个来提供电荷。

公开(公告)号：US20130058155A1

公开(公告)日：2013-03-07

申请号：US13594064

申请日：2012-08-24

Applicant: Olivier Callen ,  Anuj Grover ,  Tanmoy Roy

Inventor： Olivier Callen ,  Anuj Grover ,  Tanmoy Roy

IPC: G11C11/00

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.

Abstract translation: 6T SRAM包括反并联连接的两个反相器和两个存取晶体管，每个连接在位线和逆变器的公共节点之间。 每个逆变器包括上拉晶体管和下拉晶体管。 通过下拉晶体管栅极宽度与存取晶体管栅极宽度乘以存取晶体管栅极长度与下拉晶体管栅极长度的比率形成的乘积小于1。 此外，上拉晶体管栅极宽度大于或等于下拉晶体管栅极宽度。

公开(公告)号：US20130033289A1

公开(公告)日：2013-02-07

申请号：US13243367

申请日：2011-09-23

Applicant: Sushrant MONGA

Inventor： Sushrant MONGA

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract translation: 具有输入和输出缓冲器的系统包括动态驱动器参考发生器，用于基于数据信号和IO缓冲器电源电压产生动态驱动器参考信号;电平移位器，用于部分地基于动态驱动器参考产生电平移位信号 信号，以及具有至少一个应力晶体管的驱动器。 驱动器基于动态驱动器参考信号，电平移位信号和IO板的当前状态中的至少一个动态地调整应力晶体管两端的电压。

公开(公告)号：US20130007548A1

公开(公告)日：2013-01-03

申请号：US13175530

申请日：2011-07-01

Applicant: Nishu KOHLI

Inventor： Nishu KOHLI

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G11C29/10 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318371 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/34 ,  G11C11/4063 ,  G11C29/00 ,  G11C29/14 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

公开(公告)号：US20130003905A1

公开(公告)日：2013-01-03

申请号：US13174574

申请日：2011-06-30

Applicant: Abhishek JAIN ,  Kallol CHATTERJEE ,  Chittoor PARTHASARATHY ,  Saurabh Kumar SINGH

Inventor： Abhishek JAIN ,  Kallol CHATTERJEE ,  Chittoor PARTHASARATHY ,  Saurabh Kumar SINGH

IPC: H04L7/02

CPC classification number: H03K5/1534 ,  H03K19/00346

Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

Abstract translation: 检测器的实施例包括第一和第二发生器。 第一发生器可操作以接收第一信号的转换并且响应于转换而产生具有近似等于检测窗口的长度的长度的第一脉冲。 并且第二发生器可操作以响应于在检测窗口期间大致发生的第二信号的转变而接收第二信号并产生与第一脉冲具有关系的第二脉冲。