公开(公告)号：US20220374375A1

公开(公告)日：2022-11-24

申请号：US17882808

申请日：2022-08-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Younghyeok KIM ,  Hana YANG

IPC分类号： G06F13/28 ,  G06F3/16 ,  G06F1/10

摘要： In a method of operating an audio subsystem and a universal serial bus (USB) module, the audio subsystem receives a reference clock signal from the USB module. A USB direct memory access (UDMA) block included in the audio subsystem performs an automatic restart every predetermined period in synchronization with the reference clock signal. The UDMA block transmits data having a predetermined size to the USB module by performing a direct memory access (DMA) operation whenever the automatic restart is performed.

公开(公告)号：US11509411B2

公开(公告)日：2022-11-22

申请号：US16825180

申请日：2020-03-20

申请人： Wipro Limited

发明人： Jimmy Vincent

IPC分类号： H04J3/06 ,  G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  H04L69/28 ,  H04L43/0852

摘要： The disclosure relates to method and system for correcting a clock skew in a slave device using a precision time protocol (PTP). The method includes determining an uplink delay and a downlink delay, based on at least two packet transactions in the PTP protocol and conducted between the slave device and a master device within a pre-defined accumulator time window. The method further includes determining a change in the uplink/downlink delay with respect to a reference uplink/downlink delay. The reference uplink/downlink delay correspond to a first pre-defined accumulator time window at a start of the slave device, or to a last pre-defined accumulator time window during a previous correction of the clock skew. The method further includes correcting the clock skew upon determining the change in the uplink delay to be about same in magnitude as and to be in opposite direction to the change in the downlink delay.

公开(公告)号：US11480993B2

公开(公告)日：2022-10-25

申请号：US17214594

申请日：2021-03-26

申请人： ALTERA CORPORATION

发明人： Mark Bourgeault

IPC分类号： G06F1/10 ,  H03K19/173 ,  G06F30/39 ,  G06F30/331 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F1/06 ,  H03L7/07 ,  H03K3/037

摘要： An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US11455002B1

公开(公告)日：2022-09-27

申请号：US17331967

申请日：2021-05-27

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： Neil Whyte ,  Andy Brewster ,  Angus Black

IPC分类号： G06F1/12 ,  G06F1/08 ,  G06F1/10

摘要： A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.

公开(公告)号：US11437998B2

公开(公告)日：2022-09-06

申请号：US17186256

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kam-Tou Sio ,  Jiun-Wei Lu

IPC分类号： H03K19/17736 ,  H03K19/17784 ,  G06F1/10

摘要： An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

公开(公告)号：US11435818B2

公开(公告)日：2022-09-06

申请号：US17340878

申请日：2021-06-07

申请人： Google LLC

发明人： Mikhail Popovich ,  Gregory Sizikov

IPC分类号： G06F1/3296 ,  G06F1/10 ,  G06F1/06 ,  G06F1/08

摘要： Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

公开(公告)号：US20220269305A1

公开(公告)日：2022-08-25

申请号：US17653398

申请日：2022-03-03

申请人： SigmaSense, LLC.

发明人： Richard Stuart Seger, JR. ,  Daniel Keith Van Ostrand ,  Gerald Dale Morrison ,  Timothy W. Markison

IPC分类号： G06F1/10 ,  H03M1/12 ,  H03K19/17784 ,  H04B1/00

摘要： A method executable by a low voltage drive circuit (LVDC) includes receiving an analog receive signal, converting the analog receive signal into analog inbound data, converting the analog inbound data into digital inbound data, filtering the digital inbound data to produce filtered digital data, sampling and holding an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value, adjusting formatting of the n-bit sampled digital data value to produce a formatted digital value, and generating a packet of received digital data from a plurality of formatted digital values.

公开(公告)号：US20220247353A1

公开(公告)日：2022-08-04

申请号：US17665492

申请日：2022-02-05

申请人： FUTUREWEI TECHNOLOGIES, INC.

发明人： Michael Bushman ,  James Caldwell

IPC分类号： H03B5/12 ,  H03L7/099 ,  G06F1/10 ,  H03F1/38

摘要： A resonant tank includes a first capacitor formed on a semiconductor substrate, a first inductor formed on the semiconductor substrate, a second capacitor formed on the semiconductor substrate, and a second inductor formed on the semiconductor substrate. The first capacitor, the first inductor, the second capacitor, and the second inductor are connected in a ring configuration, with each capacitor connected between a pair of the inductors and with each inductor connected between a pair of the capacitors. An amplifier circuit is coupled to the resonant tank and configured to amplify a signal in the resonant tank.

公开(公告)号：US20220244767A1

公开(公告)日：2022-08-04

申请号：US17726924

申请日：2022-04-22

申请人： Marvell Asia Pte Ltd

发明人： Avinash Sodani ,  Srinivas Sripada ,  Ramacharan Sundararaman ,  Chia-Hsin Chen ,  Nikhil Jayakumar

IPC分类号： G06F1/26 ,  G06F1/10

摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

公开(公告)号：US20220221844A1

公开(公告)日：2022-07-14

申请号：US17148959

申请日：2021-01-14

申请人： FISHER-ROSEMOUNT SYSTEMS, INC.

发明人： Anthony Amaro, JR. ,  Mark J. Nixon

IPC分类号： G05B19/418 ,  H04L12/26 ,  G06F1/10

摘要： A first component of a process control loop (e.g., a controller or I/O gateway) monitors for and detects performance degradation of a second component of the loop by sending heartbeat messages to the second component via a diagnostic channel different from a control communications channel via which the first and second components communicate control messages for controlling an industrial process. The second component utilizes its control message interpreter to return received heartbeat messages to the first component via the diagnostic channel. The first component detects degradation of the second component when the round trip time (RTT) of a heartbeat message falls outside of an acceptable range of RTTs for the second component, and may suggest or automatically initiate mitigating actions. The first component may determine the average RTT or expected response time of the second component and acceptable range of variations based on a sample number of measured RTTs.