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101.发明申请公开(公告)号：US20200258911A1
公开(公告)日：2020-08-13
申请号：US16861939
申请日：2020-04-29
发明人： Bong-soon LIM , Jin-young KIM , Sang-won SHIM , Il-han PARK
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11575 , G11C16/08 , H01L27/11565 , H01L23/522 , G11C16/04 , H01L23/535 , H01L25/18 , H01L27/11573
摘要： A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.
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公开(公告)号：US10741574B2
公开(公告)日：2020-08-11
申请号：US15955256
申请日：2018-04-17
发明人： Kwangyoung Jung , Jongwon Kim , Dongseog Eun , Joonhee Lee
IPC分类号： H01L27/11568 , H01L27/11582 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11575
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.
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公开(公告)号：US10734402B2
公开(公告)日：2020-08-04
申请号：US15909371
申请日：2018-03-01
发明人： Kenichi Yoshikawa
IPC分类号： H01L21/3213 , H01L27/11582 , H01L27/11556 , H01L27/11575 , H01L27/1157 , H01L21/311
摘要： A method of fabricating a semiconductor device is described. A plurality of first films and a plurality of second films are alternately formed on a substrate. A hole is formed in the first and second films. A first metal layer is formed on a surface of the hole. The first metal layer is removed from a bottom surface of the hole. A second metal layer may be formed on a surface of the first metal layer after removing the first metal layer from the bottom surface of the hole. The bottom of the hole exposed from the first and second metal layers may be processed to increase a depth of the hole.
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公开(公告)号：US20200235115A1
公开(公告)日：2020-07-23
申请号：US16842698
申请日：2020-04-07
发明人： Jun Liu
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.
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公开(公告)号：US20200235003A1
公开(公告)日：2020-07-23
申请号：US16838648
申请日：2020-04-02
发明人： Chung-II HYUN , Semee JANG , Sung Yun LEE
IPC分类号： H01L21/768 , H01L27/11575 , H01L27/11582 , H01L27/1157
摘要： A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.
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公开(公告)号：US10720213B2
公开(公告)日：2020-07-21
申请号：US15780607
申请日：2016-12-19
发明人： Hiroyuki Ogawa , Fumiaki Toyama , Takuya Ariki
IPC分类号： G11C16/08 , G11C5/02 , H01L27/11565 , H01L27/11575 , G11C16/04 , H01L23/522 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , G11C8/10
摘要： The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
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公开(公告)号：US10700082B2
公开(公告)日：2020-06-30
申请号：US16286207
申请日：2019-02-26
发明人： Go Oike
IPC分类号： H01L27/11575 , H01L27/11519 , H01L27/11565 , H01L27/11582 , H01L21/768 , H01L27/11556 , H01L23/522 , H01L27/11548
摘要： A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.
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108.发明授权公开(公告)号：US10700078B1
公开(公告)日：2020-06-30
申请号：US16278488
申请日：2019-02-18
发明人： Zhixin Cui , Masatoshi Nishikawa , Yanli Zhang
IPC分类号： H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11529 , H01L27/11519 , H01L27/11575 , H01L27/11578 , H01L21/28
摘要： A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
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公开(公告)号：US10700004B2
公开(公告)日：2020-06-30
申请号：US15960106
申请日：2018-04-23
发明人： Shih-Hung Chen
IPC分类号： H01L23/528 , H01L27/11519 , H01L27/11575 , H01L27/11565 , H01L27/11548 , H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11582
摘要： A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.
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公开(公告)号：US10685695B2
公开(公告)日：2020-06-16
申请号：US16405219
申请日：2019-05-07
发明人： Chang Hoon Jeon , Yong Seok Kim , Jun Hee Lim
IPC分类号： G11C5/02 , G11C11/40 , G11C16/04 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/49 , H01L29/51
摘要： A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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