公开(公告)号：US06747908B2

公开(公告)日：2004-06-08

申请号：US10172314

申请日：2002-06-13

Applicant: Chan-Yong Lee ,  Jung-Bae Lee

Inventor： Chan-Yong Lee ,  Jung-Bae Lee

IPC: G11C800

CPC classification number: G11C8/14 ,  G11C8/10

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the previous neighboring partial blocks; and a control means for selecting sub word lines of a corresponding partial block and sub word lines of a neighboring partial block connected to the sub word lines of the corresponding partial block when the corresponding partial block is selected in response to externally applied row and column address.

Abstract translation: 半导体存储器件包括多个存储单元阵列块，每个存储单元阵列块包括与多个全局字线中的每一个对应的多个部分块，多个全局字线和奇数和偶数子字线， 所述多个部分块中的每个奇数部分块的奇数子字线分别连接到每个先前相邻部分块的奇数子字线，偶数子字线 分别连接到每个下一个相邻部分块的偶数子字线的多个部分块中的每个奇数部分块，偶数编号的奇数子字线 分别连接到下一个相邻部分块中的每一个的奇数子字线的多个部分块中的部分块，偶数的偶数子字线 分别连接到每个先前相邻部分块的偶数子字线的多个部分块中的数个部分块; 以及控制装置，用于当响应于外部施加的行和列地址选择对应的部分块时，选择连接到对应的部分块的子字线的相邻部分块的相应部分块和子字线的子字线 。

公开(公告)号：US06337809B1

公开(公告)日：2002-01-08

申请号：US09543759

申请日：2000-04-05

Applicant: Kun-tae Kim ,  Jung-bae Lee

Inventor： Kun-tae Kim ,  Jung-bae Lee

IPC: G11C1604

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device is provided that is capable of increasing a data processing speed and the efficiency of a data input and output pin. A method is also provided for controlling the read and write of such a device. A data first-in first-out (FIFO) circuit temporarily stores write data when a read command is received during a write operation and outputs the stored write data to the memory cell array after a read operation is completed. An address FIFO circuit temporarily stores addresses corresponding to the write data when the read command is received during the write operation and outputs the stored addresses to the memory cell array after the read operation is completed. A control signal generator generates a plurality of control signals for controlling the data FIFO circuit and the address FIFO circuit in response to a write command and the read command. When the addresses received during the read operation coincide with the addresses stored in the address FIFO circuit, data is not output from the memory cell array, but instead, the write data stored in the data FIFO circuit is output. The number of write data items stored in the data FIFO circuit and the number of addresses stored in the address FIFO circuit vary according to the column address strobe (CAS) latency of the semiconductor memory device.

Abstract translation: 提供了能够提高数据处理速度和数据输入输出引脚的效率的半导体存储器件。 还提供了一种用于控制这种设备的读取和写入的方法。 数据先进先出（FIFO）电路在写入操作期间接收到读命令时临时存储写数据，并且在读操作完成之后将存储的写数据输出到存储单元阵列。 当写操作期间接收到读命令时，地址FIFO电路临时存储对应于写数据的地址，并且在读操作完成之后将存储的地址输出到存储单元阵列。 控制信号发生器响应于写入命令和读取命令产生用于控制数据FIFO电路和地址FIFO电路的多个控制信号。 当读操作期间接收的地址与存储在地址FIFO电路中的地址一致时，不从存储单元阵列输出数据，而是输出存储在数据FIFO电路中的写入数据。 存储在数据FIFO电路中的写数据项数和存储在地址FIFO电路中的地址数根据半导体存储器件的列地址选通（CAS）延迟而变化。

公开(公告)号：US06262938B1

公开(公告)日：2001-07-17

申请号：US09518144

申请日：2000-03-03

Applicant: Jung-bae Lee ,  Choong-sun Shin ,  Dong-yang Lee

Inventor： Jung-bae Lee ,  Choong-sun Shin ,  Dong-yang Lee

IPC: G11C800

CPC classification number: G11C8/18 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078

Abstract: A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal. It is therefore possible to appropriately perform a posted CAS latency operation and a general CAS latency operation by the SDRAM without an additional MRS command according to this SDRAM and the method of controlling the CAS latency.

Abstract translation: 提供具有发布的列存取选通（CAS）等待时间的同步DRAM（SDRAM）和控制CAS等待时间的方法。 为了控制从CAS命令和列地址的应用到存储器开始的延迟时间，以时钟周期为单位的读取或写入操作，将延迟时间编程为模式寄存器集（MRS）的第一种方法， 并且提供了使用内部信号和外部信号来检测延迟时间的第二种方法。 在第二种方法中，SDRAM可以包括用于控制CAS等待时间的计数器。 该计数器通过根据在同一存储体中产生行访问命令到列访问命令的时钟信号的时钟周期数来产生用于控制CAS等待时间的信号来控制SDRAM的CAS延迟，并读取 信号。 因此，根据该SDRAM和控制CAS等待时间的方法，可以适当地执行通过SDRAM而没有附加MRS命令的SDRAM的CAS延迟操作和一般的CAS等待时间操作。

公开(公告)号：US09130557B2

公开(公告)日：2015-09-08

申请号：US14093916

申请日：2013-12-02

Applicant: Young Chul Cho ,  Jung Bae Lee ,  Jung Hwan Choi

Inventor： Young Chul Cho ,  Jung Bae Lee ,  Jung Hwan Choi

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

CPC classification number: G06F13/16 ,  G05F1/625 ,  G06F1/3287 ,  G06F13/4068 ,  G06F13/4221 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract translation: 操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。 另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。 另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

公开(公告)号：US20140013183A1

公开(公告)日：2014-01-09

申请号：US13915179

申请日：2013-06-11

Applicant: Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

IPC: G06F11/10

CPC classification number: G06F11/1012 ,  G06F11/10 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G11C2029/0411 ,  H03M13/3707

Abstract: An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

Abstract translation: 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。

公开(公告)号：US08483683B2

公开(公告)日：2013-07-09

申请号：US11873854

申请日：2007-10-17

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H04W4/00

CPC classification number: H04W48/16 ,  H04W8/183

Abstract: A method and an apparatus for connecting a network in a portable terminal. The method for connecting a network in a portable terminal includes searching a network from which a signal is received, receiving network identifying information from the searched network, retrieving connection information corresponding to the network identifying information, from network connection information stored in the portable terminal in advance, and setting the retrieved network connection information as the network connection information of the portable terminal.

Abstract translation: 一种用于连接便携式终端中的网络的方法和装置。 用于连接便携式终端中的网络的方法包括从存储在便携式终端中的网络连接信息中搜索从哪个接收到信号的网络，从所搜索的网络接收网络识别信息，检索与网络识别信息相对应的连接信息 提前，并将所检索的网络连接信息设置为便携式终端的网络连接信息。

公开(公告)号：US08278992B2

公开(公告)日：2012-10-02

申请号：US12845279

申请日：2010-07-28

Applicant: So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

Inventor： So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

IPC: G05F1/10

CPC classification number: G11C5/14

Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。

公开(公告)号：US08234532B2

公开(公告)日：2012-07-31

申请号：US13221418

申请日：2011-08-30

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G08C25/02

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US08185711B2

公开(公告)日：2012-05-22

申请号：US11723821

申请日：2007-03-22

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

IPC: G06F12/00

CPC classification number: G06F13/1668

Abstract: A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.

Abstract translation: 存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法。 示例性存储器模块可以包括多个存储单元，每个存储器单元具有接口和至少一个存储器件。 示例性写入操作方法可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，提取命令信号，地址和写入数据 如果接收到的分组命令对应于写入操作，则接收到的分组命令，通过给定一个存储器单元内部的写入/读取数据线将提取的写入数据传送到至少一个存储器件，并将传送的写入数据写入至少一个 存储设备。 示例性读取操作可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，从接收到的分组命令中提取命令信号和地址 如果接收的分组命令对应于读取操作，则将所提取的命令信号和地址传送到至少一个存储器件，通过内部的写入/读取数据线从至少一个存储器件接收与所提取的命令信号和地址相对应的读取数据 到给定的一个存储器单元，并且通过给定的一个存储器单元外部的读取数据线从接口发送接收到的读取数据。

公开(公告)号：US08174921B2

公开(公告)日：2012-05-08

申请号：US12589674

申请日：2009-10-27

Applicant: Ho-Young Kim ,  Jung-Bae Lee

Inventor： Ho-Young Kim ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C29/02 ,  G11C5/143 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.

Abstract translation: 半导体存储器件包括多个存储体; 多个温度检测电路和共享控制电路。 温度感测电路对应于存储体，并且各自设置在相应的存储体的附近。 共享控制电路连接到多个温度检测电路和多个刷新电路，用于刷新多个存储体，对多个温度感测电路进行校准，对用于分别控制多个温度感测电路的刷新间隔的信号进行数字处理 的存储体，并且将处理的信号发送到多个刷新电路。 因此，单独或选择性地控制各通道或组的刷新间隔。 此外，由于多个温度感测电路连接到共享温度控制电路，所以芯片中的电路的占用面积减小或最小化。