公开(公告)号：US20090175063A1

公开(公告)日：2009-07-09

申请号：US12344765

申请日：2008-12-29

申请人： Duk-Ha PARK ,  Ki-Whan SONG

发明人： Duk-Ha PARK ,  Ki-Whan SONG

IPC分类号： G11C5/06 ,  G11C7/06 ,  G11C8/08

CPC分类号： G11C11/404 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L29/7841

摘要： A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括具有多个单元块的单元阵列。 每个单元块包括沿一个方向布置的源极和字线，沿垂直方向排列的位线，以及具有相应浮体的存储单元。 相邻的存储单元分别共享源极或漏极区域以形成共同的源极或漏极区域。 源极区域以字线方向排列并连接到相应的源极线，并且漏极区域以位线方向排列并连接到相应的位线。 存储器单元的栅极被排列在字线方向上并被连接以形成字线。 源极线形成在字线的一层上，位线形成在与字线和源极线绝缘的不同层上。

公开(公告)号：US07548447B2

公开(公告)日：2009-06-16

申请号：US11604823

申请日：2006-11-28

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C11/24 ,  G11C11/34 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each other, at least one bit line oriented in the first direction and at least one drain positioned between the first and second source lines and the at least one bit line. A first example method may include applying a first voltage to a source line, connected to the memory cell, during a write operation of the memory cell and applying a second voltage to the source line during a read operation of the memory cell, the first and second voltages not being the same and the second voltage not being a ground voltage. A second example method may include applying a first positive voltage to a word line, applying a second positive voltage to a source line, detecting a voltage at a bit line, the detected bit line voltage based on the applied first and second positive voltages and determining whether the memory cell stores data at a first logic level or a second logic level based on the detected bit line voltage.

摘要翻译： 一种半导体存储器件及其方法。 示例性半导体存储器件可以包括半导体衬底，第一源极线和在第一方向上定向的第二源极线，第一和第二源极线彼此不接触，至少一个位于第一方向的位线和 位于第一和第二源极线与至少一个位线之间的至少一个漏极。 第一示例性方法可以包括在存储器单元的写入操作期间向连接到存储器单元的源极线施加第一电压，并且在存储器单元的读取操作期间向源极线施加第二电压，第一和 第二电压不相同，第二电压不是接地电压。 第二示例性方法可以包括将第一正电压施加到字线，向源极线施加第二正电压，基于施加的第一和第二正电压检测位线上的电压，检测到的位线电压，并确定 存储单元是否基于检测到的位线电压将数据存储在第一逻辑电平或第二逻辑电平。

公开(公告)号：US07442988B2

公开(公告)日：2008-10-28

申请号：US11604943

申请日：2006-11-28

申请人： Chang-Woo Oh ,  Ki-Whan Song

发明人： Chang-Woo Oh ,  Ki-Whan Song

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785

摘要： Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.

摘要翻译： 公开了半导体器件及其制造方法。 该器件设置在基板上，包括由第一和第二侧壁构成的鳍片，在鳍片的第一侧壁上以间隔物图案形成的第一栅极线和形成在第二栅极上的间隔物图案中的第二栅极线 鳍的侧壁 第一和第二杂质区域设置在翅片中。 第一和第二杂质区彼此隔离并且在第一和第二栅极线之间的鳍中限定沟道区。

公开(公告)号：US07433223B2

公开(公告)日：2008-10-07

申请号：US11546421

申请日：2006-10-12

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

IPC分类号： G11C11/24

CPC分类号： G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

摘要： In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

摘要翻译： 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

公开(公告)号：US20080130376A1

公开(公告)日：2008-06-05

申请号：US11943653

申请日：2007-11-21

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016

摘要： A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source line to store data. A controller applies a first voltage to the common source line, a negative second voltage to the word line, a third voltage as a first sense enable control voltage and the first voltage as a second sense enable control voltage during a first write period of a write operation. The controller also applies a fourth voltage to the common source line and the first voltage to the word line during a second write period of the write operation. The sensing portion amplifies a bit line and an inverted bit line to the third voltage or the first voltage, respectively, during the first write period in response to the first and second sense enable control voltages.

摘要翻译： 半导体存储器件包括具有浮体的第一和第二存储单元，每个浮体包括连接到字线的栅极和连接到公共源极线以存储数据的电极。 控制器在写入的第一写入周期期间将第一电压施加到公共源极线，对字线施加负的第二电压，将第三电压作为第一感测使能控制电压施加第一电压，将第一电压作为第二感测使能控制电压 操作。 在写入操作的第二写入周期期间，控制器还向公共源极线施加第四电压并将第一电压施加到字线。 响应于第一和第二感测使能控制电压，感测部分在第一写入周期期间分别将位线和反相位线放大到第三电压或第一电压。

公开(公告)号：US20080123439A1

公开(公告)日：2008-05-29

申请号：US11882932

申请日：2007-08-07

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4099 ,  G11C2207/002

摘要： One embodiment includes a plurality of word lines, a plurality of source lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells is a floating body cell. A gate of each floating body cell is connected to one of the word lines, a drain of each floating body cell is connected to one of the bit lines, and a source of each floating body cell is connected to one of the source lines. At least one bit line and source line selecting circuit is configured to selectively connect each of the plurality of bit lines to a first output bit line and to selectively connect the source lines to a source voltage. At least one sense amplifier is configured to sense data based on a voltage on the first output bit line.

摘要翻译： 一个实施例包括多个字线，多个源极线，与多个字线相交的多个位线，以及形成在多条字线和多条位线的交点处的多个存储单元。 多个存储单元中的每一个都是浮体单元。 每个浮体单元的栅极连接到一个字线，每个浮体单元的漏极连接到一个位线，并且每个浮体单元的源极连接到源极线之一。 至少一个位线和源极线选择电路被配置为选择性地将多个位线中的每一个连接到第一输出位线并且选择性地将源极线连接到源极电压。 至少一个读出放大器被配置为基于第一输出位线上的电压来感测数据。

公开(公告)号：US20070158727A1

公开(公告)日：2007-07-12

申请号：US11649074

申请日：2007-01-03

申请人： Ki-Whan Song ,  Chang-Hyun Kim

发明人： Ki-Whan Song ,  Chang-Hyun Kim

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/10802 ,  H01L27/108 ,  H01L27/10844 ,  H01L29/7841

摘要： A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film on the insulating layer and surrounding the charge storage region. A body region of the first conductivity type is on an upper surface of the charge storage region, and a gate stack including a gate electrode and a gate insulating film is on the body region. A source region and a drain region of a second conductivity type are on opposite sides of the body region. The charge storage region extends further towards the semiconductor substrate than the source region and/or the drain region. Methods of forming semiconductor memory devices are also disclosed.

摘要翻译： 半导体存储器件包括：半导体衬底，包括绝缘层，绝缘层上的第一导电类型的电荷存储区域和绝缘层上的绝缘膜并且围绕电荷存储区域。 第一导电类型的体区在电荷存储区的上表面上，并且包括栅电极和栅极绝缘膜的栅堆叠在身体区域上。 第二导电类型的源极区域和漏极区域在身体区域的相对侧上。 电荷存储区域比源极区域和/或漏极区域进一步向着半导体衬底延伸。 还公开了形成半导体存储器件的方法。

公开(公告)号：US20070138524A1

公开(公告)日：2007-06-21

申请号：US11604823

申请日：2006-11-28

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： H01L29/94 ,  H01L21/8244

CPC分类号： H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each other, at least one bit line oriented in the first direction and at least one drain positioned between the first and second source lines and the at least one bit line. A first example method may include applying a first voltage to a source line, connected to the memory cell, during a write operation of the memory cell and applying a second voltage to the source line during a read operation of the memory cell, the first and second voltages not being the same and the second voltage not being a ground voltage. A second example method may include applying a first positive voltage to a word line, applying a second positive voltage to a source line, detecting a voltage at a bit line, the detected bit line voltage based on the applied first and second positive voltages and determining whether the memory cell stores data at a first logic level or a second logic level based on the detected bit line voltage.

摘要翻译： 一种半导体存储器件及其方法。 示例性半导体存储器件可以包括半导体衬底，第一源极线和在第一方向上定向的第二源极线，第一和第二源极线彼此不接触，至少一个位于第一方向的位线和 位于第一和第二源极线与至少一个位线之间的至少一个漏极。 第一示例性方法可以包括在存储器单元的写入操作期间向连接到存储器单元的源极线施加第一电压，并且在存储器单元的读取操作期间向源极线施加第二电压，第一和 第二电压不相同，第二电压不是接地电压。 第二示例性方法可以包括将第一正电压施加到字线，向源极线施加第二正电压，基于所施加的第一和第二正电压检测位线上的电压，以及确定检测到的位线电压 存储单元是否基于检测到的位线电压将数据存储在第一逻辑电平或第二逻辑电平。

公开(公告)号：US20070069310A1

公开(公告)日：2007-03-29

申请号：US11525021

申请日：2006-09-22

申请人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park

发明人： Ki-Whan Song ,  Jong-Duk Lee ,  Byung-Gook Park

IPC分类号： H01L29/76

CPC分类号： H01L29/7436 ,  H01L27/0262

摘要： A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a second portion formed within the substrate. A fourth junction region may include a first portion formed within the second well and a second portion formed within the substrate. A gate electrode may be formed on the substrate between the third junction region and the fourth junction region. A fifth junction region may be formed within a region of the substrate.

摘要翻译： 可控硅整流器（SCR）可以包括在衬底内形成的第一阱和第二阱。 第一接合区域和第二接合区域可以形成在第一阱内。 第三结区域可以包括形成在第一阱内的第一部分和形成在衬底内的第二部分。 第四结区域可以包括形成在第二阱内的第一部分和形成在衬底内的第二部分。 可以在第三接合区域和第四接合区域之间的衬底上形成栅电极。 第五结区域可以形成在衬底的区域内。