公开(公告)号：US06943126B1

公开(公告)日：2005-09-13

申请号：US10314381

申请日：2002-12-06

Applicant: Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0217 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/28176 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/76834 ,  H01L29/518

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract translation: 形成半导体结构的方法包括在叠层上形成包含氮化物的蚀刻停止层。 堆叠在半导体衬底上，堆叠包括（i）栅极层。 通过CVD形成是用包含第二化合物的气体，该第一化合物是Si x L 2 x X 2，以及包含氮和氘的第二化合物，L是氨基，X是 是1或2。

公开(公告)号：US06817903B1

公开(公告)日：2004-11-16

申请号：US09635507

申请日：2000-08-09

Applicant: Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

Inventor： Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

IPC: H01L21311

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/31662 ,  H01L21/76205 ,  H01L21/76224

Abstract: A method and process reducing or eliminating electrical leakage between active areas in a semiconductor separated by isolation regions. A method and process are disclosed for the fabrication of an isolation region in a semiconductor. The method and process can be used in the fabrication of isolation regions used for the separation of adjacent active areas in an integrated circuit. A shallow trench is created on the surface of the semiconductor in regions where isolation spaces are to be formed. A layer of silicon dioxide (LINOX) is then grown over the surfaces of the trench. The LINOX covers roughened regions formed along the surfaces of the trench during its formation. The LINOX is then annealed at a temperature above the LINOX deposition temperature for a period of time. Annealing reduces stresses in the LINOX and in the surrounding semiconductor material. Annealing also increases the density of the LINOX. Thus annealing increases the LINOX resistance to gouge during subsequent processing. This leads to a reduction in dislocations in the semiconductor and a reduction in electrical leakage around the isolation region. A more robust LINOX and a reduction in electrical leakage around an isolation region allows the further shrinkage of integrated circuit dimensions. Furthermore, denuding and gettering of the semiconductor are both accomplished during the annealing step which results in a shortening of total processing time. Finally, since gouging of the LINOX no longer occurs where poly/spacer etch overlaps an active area corner, restrictions on placement of poly lines have been eliminated.

Abstract translation: 一种减少或消除由隔离区隔开的半导体的有源区之间的漏电的方法和过程。 公开了用于制造半导体中的隔离区域的方法和工艺。 该方法和过程可用于制造用于在集成电路中分离相邻有源区的隔离区。 在要形成隔离空间的区域中，在半导体的表面上形成浅沟槽。 然后在沟槽的表面上生长一层二氧化硅（LINOX）。 LINOX包括在其形成期间沿着沟槽的表面形成的粗糙区域。 然后将LINOX在高于LINOX沉积温度的温度下退火一段时间。 退火降低了LINOX和周围半导体材料的应力。 退火也增加了LINOX的密度。 因此，退火在后续加工过程中增加了LINOX电阻。 这导致半导体中位错的减少和隔离区周围的漏电减少。 更强大的LINOX和隔离区域周围的漏电减少允许集成电路尺寸进一步收缩。 此外，半导体的剥蚀和吸杂都在退火步骤期间完成，这导致总处理时间的缩短。 最后，由于在多层/间隔层蚀刻与有源区域角重叠的情况下，LINOX的刨削不再发生，所以已经消除了对多线的布置的限制。

公开(公告)号：US06794269B1

公开(公告)日：2004-09-21

申请号：US10324989

申请日：2002-12-20

Applicant: Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

Inventor： Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

IPC: H01L2176

CPC classification number: H01L21/763 ,  H01L21/76202

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

Abstract translation: 提供了一种方法，其包括在半导体形貌内形成深度隔离结构。 在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。 此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。 在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。 在这样的实施例中，沟槽的空缺部分可以填充第二填充层。 在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

公开(公告)号：US06677213B1

公开(公告)日：2004-01-13

申请号：US10094108

申请日：2002-03-08

Applicant: Krishnaswamy Ramkumar ,  Frederick B. Jenne

Inventor： Krishnaswamy Ramkumar ,  Frederick B. Jenne

IPC: H01L21336

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

Abstract translation: 提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。 特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。 在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。 另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。 在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。 在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。

公开(公告)号：US06660661B1

公开(公告)日：2003-12-09

申请号：US10183095

申请日：2002-06-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21469

CPC classification number: H01L21/32051 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76838

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 低k电介质有助于降低金属线在最后一个金属电平的电容，这可能刚好低于钝化水平。 在另一个实施例中，金属线相对较厚。 这有助于降低金属线的电阻并导致RC延迟。

公开(公告)号：US06534378B1

公开(公告)日：2003-03-18

申请号：US09143899

申请日：1998-08-31

Applicant: Krishnaswamy Ramkumar ,  Chidambaram G. Kallingal ,  Sriram Madhavan

Inventor： Krishnaswamy Ramkumar ,  Chidambaram G. Kallingal ,  Sriram Madhavan

IPC: H01L2358

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: The present invention advantageously provides a method for retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent processing steps. According to an embodiment, alignment marks are etched into a semiconductor substrate. Thereafter, a pad oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. Isolation trenches which are deeper than the alignment mark trenches are formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A substantially transparent dielectric, e.g., oxide, is then deposited across the semiconductor topography to a level spaced above the first nitride layer. In this manner, both the isolation trenches and the alignment mark trenches are filled. The dielectric is then subjected to a polish that removes the dielectric above the isolation trenches to the nitride layer and the dielectric above the alignment mark trenches to a level above the nitride layer. A slurryless fixed abrasive polishing technique may be used to planarize the dielectric. A polysilicon/nitride stack which is deposited across the topography may be patterned using lithography. Light is reflected from the alignment marks to detect their positions so that a reticle can be aligned to the polysilicon/nitride stack during the lithography process.

Abstract translation: 本发明有利地提供了一种用于在抛光电介质期间将基本透明的电介质保持在对准标记之上以确保对准标记被保留用于后续处理步骤的方法。 根据实施例，对准标记被蚀刻到半导体衬底中。 此后，在衬底表面上沉积焊盘氧化物层，随后沉积第一氮化物层。 比对准标记沟槽更深的绝缘沟槽在衬底内分开形成间隔开的距离。 光学光刻可用于限定第一氮化物层，衬垫氧化物层和待蚀刻衬底的区域。 因此，隔离沟槽成为衬底氧化层和第一氮化物层未覆盖的衬底的唯一区域。 然后将基本上透明的电介质（例如氧化物）横跨半导体形貌沉积到在第一氮化物层之上间隔开的水平面上。 以这种方式，填充隔离沟槽和对准标记沟槽。 然后对电介质进行抛光，其将隔离沟槽上方的电介质移除到氮化物层和对准标记沟槽上方的电介质至氮化物层上方的电平。 可以使用无淤泥固定的研磨抛光技术来平坦化电介质。 可以使用光刻法来图案化跨越形貌的多晶硅/氮化物堆叠。 光从对准标记反射以检测它们的位置，使得在光刻过程中掩模版可以与多晶硅/氮化物堆叠对准。

公开(公告)号：US06436848B1

公开(公告)日：2002-08-20

申请号：US09281672

申请日：1999-03-30

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L2131

CPC classification number: H01L21/28202 ,  C23C8/34 ,  H01L21/3144 ,  H01L29/518

Abstract: A nitrogen-rich silicon oxide layer is formed using an apparatus for oxidizing semiconductor substrates having a process zone or chamber fluidically coupled to a torch zone or chamber. Generally, a thin initial silicon oxide layer is formed on the substrate using common wet or dry oxidizing processing conditions. Subsequently, a nitridizing atmosphere is introduced to the semiconductor substrates causing a nitrogen-rich silicon oxide layer to be formed thereon. The nitridizing atmosphere is advantageously generated by an exothermic reaction within the torch zone. Once formed, the nitridizing atmosphere is directed to the process zone through the fluidic coupling. The advantageous exothermic reaction resulting from the introduction of nitrous oxide (N2O) to the torch zone at a temperature sufficiently high to induce such an exothermic reaction, generally between approximately 850 to 950 degrees Celsius. Semiconductor integrated circuits are formed using nitrogen-rich silicon oxide films of the current method.

Abstract translation: 使用用于氧化半导体衬底的装置形成富氮氧化硅层，所述设备具有流体耦合到焊炬区或室的工艺区或腔室。 通常，使用常规的湿式或干式氧化处理条件在基板上形成薄的初始氧化硅层。 随后，将氮化气氛引入到半导体衬底中，从而在其上形成富氮氧化硅层。 氮化气氛有利地由焊炬区内的放热反应产生。 一旦形成，氮化气氛通过流体耦合导向工艺区。 通过在足够高的温度下将一氧化二氮（N 2 O）引入焊炬区而产生的有利的放热反应，引起这种放热反应，通常在约850至950摄氏度之间。 使用当前方法的富氮氧化硅膜形成半导体集成电路。

公开(公告)号：US06171180B2

公开(公告)日：2001-01-09

申请号：US09052219

申请日：1998-03-31

Applicant: William W. C. Koutny, Jr. ,  Chidambaram G. Kallingal ,  Krishnaswamy Ramkumar

Inventor： William W. C. Koutny, Jr. ,  Chidambaram G. Kallingal ,  Krishnaswamy Ramkumar

IPC: B24B2900

CPC classification number: H01L21/31053 ,  H01L21/76224

Abstract: The present invention advantageously provides a method for using an abrasive surface and a particle-free liquid to polish a dielectric, wherein the dielectric is deposited within an isolation trench and across a polish stop surface such that a recess region of the dielectric is spaced below the polish stop surface. In an embodiment, the dielectric is an isolation oxide, and the polish stop surface belongs to an upper surface of a nitride layer formed above a silicon-based substrate. The surface of the dielectric is positioned laterally adjacent the abrasive polishing surface such that the particle-free liquid is positioned at the interface between the dielectric and the polishing surface. The particle-free liquid is preferably deionized water, and the abrasive polishing surface is preferably a polymeric matrix entrained with particles composed of, e.g., ceria. A force configured perpendicular to the backside of the substrate is applied to the polishing surface to force the dielectric surface against the polishing surface while the polishing surface is being rotated relative to the dielectric. As a result, elevationally raised regions of the dielectric are polished to the recessed region of the dielectric, planarizing the dielectric surface. The polish rate of the dielectric is substantially greater than that of the polish stop surface, and thus the polishing stop layer remains intact above the substrate. The polish rate of the elevationally raised regions of the dielectric is also greater than that of the recess region of the dielectric.

Abstract translation: 本发明有利地提供了一种使用研磨表面和无颗粒的液体来抛光电介质的方法，其中电介质沉积在隔离沟槽内并穿过抛光止动表面，使得电介质的凹陷区域间隔开 抛光停止表面。 在一个实施例中，电介质是隔离氧化物，并且抛光停止表面属于在硅基衬底上形成的氮化物层的上表面。 电介质的表面位于研磨抛光表面的横向附近，使得无颗粒的液体位于电介质和抛光表面之间的界面处。 无颗粒液体优选为去离子水，研磨抛光表面优选为与例如二氧化铈组成的颗粒夹带的聚合物基质。 垂直于衬底背面的力被施加到抛光表面，以在抛光表面相对于电介质旋转时迫使电介质表面抵靠抛光表面。 结果，电介质的垂直升高的区域被抛光到电介质的凹陷区域，使电介质表面平坦化。 电介质的抛光速率基本上大于抛光止动表面的抛光速率，因此抛光停止层在基材上方保持完整。 电介质的高度升高区域的抛光速率也大于电介质凹槽区域的抛光速率。

公开(公告)号：US5830804A

公开(公告)日：1998-11-03

申请号：US673304

申请日：1996-06-28

Applicant: James M. Cleeves ,  Krishnaswamy Ramkumar

Inventor： James M. Cleeves ,  Krishnaswamy Ramkumar

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76834

Abstract: A method of encapsulating a dielectric. According to the method of the present invention, a disposable post is formed over a portion of a substrate. Next, a first dielectric layer is formed over the substrate and the disposable post. A second dielectric layer is then formed over the first dielectric layer. Next, a third dielectric layer is formed over the second dielectric layer. A portion of the third dielectric layer is then removed so as to reveal the disposable post. The disposable post is then removed to form an opening.

Abstract translation: 一种封装电介质的方法。 根据本发明的方法，在衬底的一部分上形成一次性柱。 接下来，在基板和一次性柱上形成第一介电层。 然后在第一介电层上形成第二电介质层。 接下来，在第二电介质层上形成第三电介质层。 然后去除第三介电层的一部分以露出一次性柱。 然后移除一次性柱以形成开口。