公开(公告)号：US20120018781A1

公开(公告)日：2012-01-26

申请号：US13248197

申请日：2011-09-29

Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

公开(公告)号：US20110156145A1

公开(公告)日：2011-06-30

申请号：US13042973

申请日：2011-03-08

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract translation: 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US20110156005A1

公开(公告)日：2011-06-30

申请号：US12655468

申请日：2009-12-30

Applicant: Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/772

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20110147712A1

公开(公告)日：2011-06-23

申请号：US12646589

申请日：2009-12-23

Applicant: MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY

Inventor： MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY

IPC: H01L29/772 ,  H01L29/12 ,  H01L21/335

CPC classification number: H01L29/66636 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7784

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.

Abstract translation: 公开了一种量子阱器件及其制造方法。 在一个实施例中，量子阱结构包括覆盖在衬底上的量子阱区域和包括与量子阱区域的电荷载流子的导电性相反的导电性的掺杂剂的远程计数器掺杂。 远程计数器掺杂被结合在量子阱区域附近，用于与量子阱沟道交换移动载流子，从而减小截止状态的漏电流。 在另一个实施例中，量子阱器件包括量子阱结构，其包括远程反相掺杂，覆盖量子阱结构的一部分的栅极区域和与栅极区域相邻的源极和漏极区域。 量子阱器件还可以包括包含与量子阱沟道相同导电性的掺杂剂的远程δ掺杂。

公开(公告)号：US07898041B2

公开(公告)日：2011-03-01

申请号：US11855823

申请日：2007-09-14

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Abstract translation: 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。 接触结构能够接触具有亚光刻间距的平行半导体本体。

公开(公告)号：US20100327317A1

公开(公告)日：2010-12-30

申请号：US12459262

申请日：2009-06-26

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC: H01L29/12 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/78603

Abstract: Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 在此通常描述使用大带隙阻挡层在绝缘体上提供锗的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20100213441A1

公开(公告)日：2010-08-26

申请号：US12378828

申请日：2009-02-20

Applicant: Ravi Pillarisetty ,  Titash Rakshit ,  Mantu Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

Inventor： Ravi Pillarisetty ,  Titash Rakshit ,  Mantu Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC: H01L29/80 ,  H01L21/3205

CPC classification number: H01L29/122 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7785

Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.

Abstract translation: 在半导体器件中提供量子阱（QW）层。 QW层在QW层下面的阻挡结构中设置有铍掺杂卤素层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。

公开(公告)号：US20100193771A1

公开(公告)日：2010-08-05

申请号：US12756989

申请日：2010-04-08

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/772

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20100163847A1

公开(公告)日：2010-07-01

申请号：US12347268

申请日：2008-12-31

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/12 ,  H01L21/336 ,  H01L21/18 ,  H01L21/203

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

公开(公告)号：US20100163838A1

公开(公告)日：2010-07-01

申请号：US12346554

申请日：2008-12-30

Applicant: Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yih Jin ,  Marko Radosavljevic ,  Willy Rachmady

Inventor： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yih Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC: H01L29/06 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract translation: 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。