公开(公告)号：US20060220090A1

公开(公告)日：2006-10-05

申请号：US11089247

申请日：2005-03-23

Applicant: Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Marko Radosavljevic ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/516 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.

Abstract translation: 描述半导体器件。 该半导体器件包括形成在位于衬底内的沟道上的高k栅介质层和形成在高k栅介质层上的金属栅电极。 高k栅极电介质层具有优于基于二氧化硅的栅极电介质的截止状态泄漏特性，以及优于包含各向同性材料的高k栅极电介质的导通状态迁移率特性。

公开(公告)号：US20060214237A1

公开(公告)日：2006-09-28

申请号：US11418577

申请日：2006-05-05

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L21/823828 ,  H01L21/823857

Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

公开(公告)号：US07098507B2

公开(公告)日：2006-08-29

申请号：US10879480

申请日：2004-06-30

Applicant: Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

Inventor： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/39

CPC classification number: H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US20060183277A1

公开(公告)日：2006-08-17

申请号：US10742678

申请日：2003-12-19

Applicant: Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Chris Barns ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

Inventor： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Chris Barns ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

IPC: H01L21/8234 ,  H01L21/31

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/31691 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层上形成牺牲层。 在蚀刻牺牲层之后，在牺牲层的相对侧上形成第一和第二间隔物。 在去除牺牲层以产生位于第一和第二间隔物之间​​的沟槽之后，在高k栅介质层上形成金属层。

公开(公告)号：US20060166447A1

公开(公告)日：2006-07-27

申请号：US11390892

申请日：2006-03-27

Applicant: Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

Inventor： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060160342A1

公开(公告)日：2006-07-20

申请号：US11037860

申请日：2005-01-18

Applicant: Mark Doczy ,  Lawrence Wong ,  Valery Dubin ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau

Inventor： Mark Doczy ,  Lawrence Wong ,  Valery Dubin ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau

IPC: H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 可以使用催化金属通过表面活化来填充沟槽，然后通过化学沉积种子层，然后从下向上超超融合填充来填充沟槽。

公开(公告)号：US07074680B2

公开(公告)日：2006-07-11

申请号：US10935784

申请日：2004-09-07

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060148150A1

公开(公告)日：2006-07-06

申请号：US11028167

申请日：2005-01-03

Applicant: Jack Kavalieros ,  Peter Vandervoorn ,  Kelin Kuhn ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Jack Kavalieros ,  Peter Vandervoorn ,  Kelin Kuhn ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L29/15 ,  H01L31/0312 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545

Abstract: Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the channel region which is not adversely affected by subsequent high temperature processing. For example, after already forming the source and drains and thereafter doping the channel, temperature regimes greater than 900° C. may be avoided.

Abstract translation: 可以通过去除虚设金属栅电极作为替代金属栅极工艺的一部分并且在源极和漏极已经形成之后掺杂暴露的沟道区域来实现更高迁移率的晶体管。 结果，在一些实施例中可以在沟道区域中实现逆向掺杂分布，其不受后续高温处理的不利影响。 例如，在已经形成源极并且排出并且之后掺杂通道之后，可以避免大于900℃的温度方案。

公开(公告)号：US20060121742A1

公开(公告)日：2006-06-08

申请号：US11006438

申请日：2004-12-07

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/02052 ,  H01L21/02172 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823462 ,  H01L29/495 ,  H01L29/513

Abstract: A method for making a semiconductor device is described. That method comprises applying an atomic layer chemical vapor deposition process to form a high-k gate dielectric layer directly on a hydrophobic surface of a substrate. The atomic layer chemical vapor deposition process initiates growth of the high-k gate dielectric layer in less than about twenty growth cycles.

Abstract translation: 描述制造半导体器件的方法。 该方法包括应用原子层化学气相沉积工艺以在衬底的疏水表面上直接形成高k栅介质层。 原子层化学气相沉积工艺在低于约20个生长周期中引发高k栅极电介质层的生长。

公开(公告)号：US20060091483A1

公开(公告)日：2006-05-04

申请号：US11242807

申请日：2005-10-03

Applicant: Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L21/28097 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer.