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    Gradually Changed Dummy Pattern Distribution Around TSVs
    111.
    发明申请
    Gradually Changed Dummy Pattern Distribution Around TSVs 有权

    公开(公告)号：US20250062227A1

    公开(公告)日：2025-02-20

    申请号：US18517577

    申请日：2023-11-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Yen Liu ,  Chao Yi Lin

    IPC: H01L23/528 ,  H01L23/498 ,  H01L23/522

    Abstract: A method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. The dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. The first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. The second plurality of dummy patterns have a second pattern density different from the first pattern density.

    Packages with Implantation
    115.
    发明申请
    Packages with Implantation 有权

    公开(公告)号：US20250062136A1

    公开(公告)日：2025-02-20

    申请号：US18513957

    申请日：2023-11-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Ming-Shih Yeh

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

    Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

    APPARATUS, CIRCUITS AND METHODS FOR REDUCING MISMATCH IN AN ELECTRO-OPTIC MODULATOR
    116.
    发明申请
    APPARATUS, CIRCUITS AND METHODS FOR REDUCING MISMATCH IN AN ELECTRO-OPTIC MODULATOR 有权

    公开(公告)号：US20250060645A1

    公开(公告)日：2025-02-20

    申请号：US18936859

    申请日：2024-11-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lan-Chou CHO ,  Chewn-Pu JOU ,  Min-Hsiang HSU

    IPC: G02F1/225 ,  G02F1/21

    Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.

    Self-aligned inner spacer on gate-all-around structure and methods of forming the same
    118.
    发明授权
    Self-aligned inner spacer on gate-all-around structure and methods of forming the same 有权

    公开(公告)号：US12230692B2

    公开(公告)日：2025-02-18

    申请号：US18359597

    申请日：2023-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsungyu Hung ,  Pang-Yen Tsai ,  Pei-Wei Lee

    IPC: H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L29/423

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

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