公开(公告)号：US20140167290A1

公开(公告)日：2014-06-19

申请号：US14186617

申请日：2014-02-21

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US08642438B2

公开(公告)日：2014-02-04

申请号：US13324035

申请日：2011-12-13

Applicant: Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

Inventor： Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

IPC: H01L21/20 ,  H01L21/00

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

公开(公告)号：US20130228733A1

公开(公告)日：2013-09-05

申请号：US13598244

申请日：2012-08-29

Applicant: Min Yong Lee ,  Young Ho Lee ,  Seung Beom Baek ,  Jong Chul Lee

Inventor： Min Yong Lee ,  Young Ho Lee ,  Seung Beom Baek ,  Jong Chul Lee

IPC: H01L47/00 ,  H01L21/02

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/6609 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract translation: 提供了一种电阻式存储器件及其制造方法。 电阻式存储器件包括形成在其上形成底部结构的半导体衬底上的可变电阻层，形成在可变电阻层上的下电极，形成在下电极上的开关单元和形成在开关单元上的上电极 。

公开(公告)号：US08368182B2

公开(公告)日：2013-02-05

申请号：US12573535

申请日：2009-10-05

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

IPC: H01L29/06

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526

Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

Abstract translation: 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。

公开(公告)号：US08349690B2

公开(公告)日：2013-01-08

申请号：US12649999

申请日：2009-12-30

Applicant: Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

Inventor： Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

IPC: H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

公开(公告)号：US08275088B2

公开(公告)日：2012-09-25

申请号：US12421829

申请日：2009-04-10

Applicant: Kyung-Ho Yoon ,  Hyung-Kyu Kim ,  Jae-Yong Kim ,  Young-Ho Lee ,  Kang-Hee Lee ,  Tae-Hyun Chun ,  Wang-Kee In ,  Dong-Seok Oh ,  Chang Hwan Shin ,  Kun-Woo Song

Inventor： Kyung-Ho Yoon ,  Hyung-Kyu Kim ,  Jae-Yong Kim ,  Young-Ho Lee ,  Kang-Hee Lee ,  Tae-Hyun Chun ,  Wang-Kee In ,  Dong-Seok Oh ,  Chang Hwan Shin ,  Kun-Woo Song

IPC: G21C3/34

CPC classification number: G21C3/322 ,  G21C3/3305 ,  G21C3/3315 ,  Y02E30/38

Abstract: A perforated plate support supports dual-cooled fuel rods, each of which has concentric outer and inner tubes and is coupled with upper and lower end plugs at upper and lower ends thereof, and guide thimbles, each of which is used as a passage for a control rod. The perforated plate support is formed as a support plate having the shape of a flat plate, which includes internal channel holes, each of which has a diameter corresponding to an outer diameter of the inner tube, guide thimble holes, each of which has a diameter corresponding to an outer diameter of the guide thimble, and sub-channel holes around each internal channel hole. The upper or lower end of the dual-cooled fuel rod is coupled to the support plate such that the outer diameter of the inner tube is matched with the diameter of the internal channel hole.

Abstract translation: 多孔板支撑件支撑双重冷却的燃料棒，每个燃料棒具有同心的外管和内管，并且在其上端和下端与上端和下端塞连接，导向套管每一个用作通道 控制棒。 多孔板支撑件形成为具有平板形状的支撑板，该支撑板包括内部通道孔，每个内部通道孔的直径对应于内部管的外径，导向套管孔各自具有直径 对应于导向套管的外径，以及在每个内部通道孔周围的子通道孔。 双冷却燃料棒的上端或下端与支撑板相连，使得内管的外径与内通道孔的直径相匹配。

公开(公告)号：US08253204B2

公开(公告)日：2012-08-28

申请号：US12343347

申请日：2008-12-23

Applicant: Young-Ho Lee ,  Seung-Joon Jeon ,  Tae-Hang Ahn

Inventor： Young-Ho Lee ,  Seung-Joon Jeon ,  Tae-Hang Ahn

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract translation: 半导体器件包括：衬底上的栅极图案; 在栅极图案的两侧设置在基板中的凹部图案，每个凹部图案具有在栅极图案下方延伸的侧表面; 以及填充凹陷图案的源极和漏极，并且在栅极图案下形成应变通道。

公开(公告)号：US20120206136A1

公开(公告)日：2012-08-16

申请号：US13457130

申请日：2012-04-26

Applicant: Jin Mok Kim ,  Young Ho Lee ,  Hyukchan Kwon ,  Ki Woong Kim ,  Kwon Kyu Yu

Inventor： Jin Mok Kim ,  Young Ho Lee ,  Hyukchan Kwon ,  Ki Woong Kim ,  Kwon Kyu Yu

IPC: G01R33/02

CPC classification number: G01R33/0354 ,  G01R33/035

Abstract: Provided are a flux-locked loop circuit, a flux-locked loop method and a superconducting quantum interference device (SQUID) measuring apparatus. The flux-locked loop circuit includes a pre-amplifier configured to amplify a signal output of a SQUID, an integrator configured to integrate a signal output from the pre-amplifier and output the integrated signal, an operating range expanding unit configured to initialize the integrator by comparing an output signal of the integrator with a positive or negative reference reset voltage corresponding to an external flux of a predetermined integral multiple of flux quantum, and a feedback circuit configured to supply current to eliminate a difference between the external flux applied to the SQUID and a magnetic flux corresponding to an integral multiple of the reference reset voltage according to the output signal of the integrator.

Abstract translation: 提供了一种磁通锁定环路电路，一个磁通锁定环路方法和一种超导量子干涉装置（SQUID）测量装置。 磁通锁定环电路包括：前置放大器，被配置为放大SQUID的信号输出;积分器，被配置为积分从前置放大器输出的信号并输出​​积分信号;工作范围扩展单元，被配置为初始化积分器 通过将积分器的输出信号与对应于预定的通量量子的整数倍的外部通量的正或负参考复位电压进行比较，以及反馈电路，被配置为提供电流以消除施加到SQUID的外部通量之间的差 以及根据积分器的输出信号对应于基准复位电压的整数倍的磁通量。

公开(公告)号：US08173549B2

公开(公告)日：2012-05-08

申请号：US12477468

申请日：2009-06-03

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

IPC: H01L21/302

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1052

Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches.

Abstract translation: 在半导体衬底上的蚀刻目标层上形成包括多个平行线部分的第一掩模层图案。 在第一掩模层图案和第一掩模层图案的平行线部分之间的蚀刻目标层的部分上形成牺牲层。 第二掩模层图案形成在牺牲层上，第二掩模层图案包括设置在第一掩模层图案的相邻的平行线部分之间的相应的平行线，其中第一掩模层图案和 第二掩模层图案由牺牲层分离。 形成第三掩模层图案，其包括覆盖第一掩模层图案和第二掩模层图案的线部分的相应第一和第二端的第一和第二部分，并且在第一和第二掩模层图案的线部分处具有开口 在第一和第二端之间。 使用第三掩模层图案，第一掩模层图案和第二掩模层图案作为掩模来蚀刻牺牲层和蚀刻目标层，从而在蚀刻目标层中形成多个平行的沟槽 第一和第二掩模层图案。 可以在沟槽中形成导电线。

公开(公告)号：US08142986B2

公开(公告)日：2012-03-27

申请号：US12192430

申请日：2008-08-15

Applicant: Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

Inventor： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC: G03F7/20

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

Abstract translation: 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并在第二方向上延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。