公开(公告)号：US20090263749A1

公开(公告)日：2009-10-22

申请号：US12192430

申请日：2008-08-15

申请人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

发明人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC分类号： H01L21/302 ,  G03F7/20

CPC分类号： H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

摘要： A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

摘要翻译： 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并沿第二方向延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。

公开(公告)号：US08142986B2

公开(公告)日：2012-03-27

申请号：US12192430

申请日：2008-08-15

申请人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

发明人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC分类号： G03F7/20

CPC分类号： H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

摘要： A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

摘要翻译： 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并在第二方向上延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。

公开(公告)号：US20100155906A1

公开(公告)日：2010-06-24

申请号：US12573535

申请日：2009-10-05

申请人： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

发明人： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

IPC分类号： H01L29/06

CPC分类号： H01L27/105 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526

摘要： Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

摘要翻译： 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。

公开(公告)号：US08368182B2

公开(公告)日：2013-02-05

申请号：US12573535

申请日：2009-10-05

申请人： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

发明人： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

IPC分类号： H01L29/06

CPC分类号： H01L27/105 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526

摘要： Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

摘要翻译： 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。

公开(公告)号：US08173549B2

公开(公告)日：2012-05-08

申请号：US12477468

申请日：2009-06-03

申请人： Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

发明人： Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1052

摘要： A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches.

摘要翻译： 在半导体衬底上的蚀刻目标层上形成包括多个平行线部分的第一掩模层图案。 在第一掩模层图案和第一掩模层图案的平行线部分之间的蚀刻目标层的部分上形成牺牲层。 第二掩模层图案形成在牺牲层上，第二掩模层图案包括设置在第一掩模层图案的相邻的平行线部分之间的相应的平行线，其中第一掩模层图案和 第二掩模层图案由牺牲层分离。 形成第三掩模层图案，其包括覆盖第一掩模层图案和第二掩模层图案的线部分的相应第一和第二端的第一和第二部分，并且在第一和第二掩模层图案的线部分处具有开口 在第一和第二端之间。 使用第三掩模层图案，第一掩模层图案和第二掩模层图案作为掩模来蚀刻牺牲层和蚀刻目标层，从而在蚀刻目标层中形成多个平行的沟槽 第一和第二掩模层图案。 可以在沟槽中形成导电线。

公开(公告)号：US20090321931A1

公开(公告)日：2009-12-31

申请号：US12313234

申请日：2008-11-18

申请人： Young-ho Lee ,  Jae-hwang Sim ,  Jae-Kwan Park

发明人： Young-ho Lee ,  Jae-hwang Sim ,  Jae-Kwan Park

IPC分类号： H01L23/52

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the semiconductor device maintain an insulating distance between contact plugs and wiring lines formed on the contact plugs by using an etch mask pattern for forming contact holes. The device comprises a substrate comprising a plurality of conductive areas; an inter-layer insulating layer on the substrate having a plurality of contact holes through which the conductive areas are exposed; a first insulating layer covering the top surface of the inter-layer insulating layer; a plurality of contact plugs respectively connected to the plurality of conductive areas through the plurality of contact holes, the plurality of contact plugs having top surfaces a distance from each of which to a top surface of the substrate is less than a distance from the top surface of the inter-layer insulating layer to the top surface of the substrate; a plurality of ring-shaped insulating spacers covering inner sidewalls of the inter-layer insulating layer, inner sidewalls of the first insulating layer, and outer edge areas of top surfaces of the contact plugs so as to expose center areas of the top surfaces of the contact plugs in the contact holes; and a plurality of wiring lines above the first insulating layer and on the insulating spacers and respectively electrically connected to the plurality of contact plugs.

摘要翻译： 通过使用用于形成接触孔的蚀刻掩模图案，半导体器件和制造半导体器件的方法保持接触插塞和形成在接触插塞上的布线之间的绝缘距离。 所述装置包括包括多个导电区域的基板; 所述基板上的层间绝缘层具有多个所述导电区域露出的接触孔; 覆盖所述层间绝缘层的顶表面的第一绝缘层; 分别通过所述多个接触孔连接到所述多个导电区域的多个接触插塞，所述多个接触插塞具有从所述基板的每个顶部表面到所述基板的顶表面的距离小于距所述顶表面的距离的顶表面 的层间绝缘层到基板的顶面; 多个环状绝缘垫片，其覆盖层间绝缘层的内侧壁，第一绝缘层的内侧壁和接触插塞的上表面的外缘区域，以便暴露出中间区域 接触插塞在接触孔中; 以及在第一绝缘层上方和绝缘间隔物上的多条布线，并分别电连接到多个接触插塞。

公开(公告)号：US07952549B2

公开(公告)日：2011-05-31

申请号：US11441148

申请日：2006-05-26

申请人： Young-ho Lee ,  Seung-joon Yang ,  Ki-hyun Hong

发明人： Young-ho Lee ,  Seung-joon Yang ,  Ki-hyun Hong

IPC分类号： G09G3/36

CPC分类号： G09G3/3413 ,  G09G3/342 ,  G09G2310/0235 ,  G09G2310/024 ,  G09G2310/08 ,  G09G2320/0242 ,  G09G2320/062 ,  G09G2320/0633 ,  G09G2320/064 ,  G09G2320/103 ,  G09G2340/06 ,  G09G2360/16

摘要： A field sequential display apparatus and an image display method thereof are provided. A field sequential display apparatus includes: a color-coordinate conversion unit which analyses image state information of a plurality of input image signals of primary colors representing one image and converts the input image signals of primary colors into image signals of primary colors and at least one image signal of specific colors by using the image state information; a display panel displaying the converted image signals; and a light source driving unit which sequentially drives light sources corresponding to colors of the converted image signals. Accordingly, color breakup can be prevented, and image quality can be improved.

摘要翻译： 提供场顺序显示装置及其图像显示方法。 场顺序显示装置包括：颜色坐标转换单元，分析表示一个图像的原色的多个输入图像信号的图像状态信息，并将原色的输入图像信号转换为原色的图像信号和至少一个 通过使用图像状态信息的特定颜色的图像信号; 显示转换后的图像信号的显示面板; 以及光源驱动单元，其顺序地驱动与转换的图像信号的颜色对应的光源。 因此，可以防止颜色分解，并且可以提高图像质量。

公开(公告)号：US07675572B2

公开(公告)日：2010-03-09

申请号：US11237959

申请日：2005-09-29

申请人： Young-ho Lee ,  Seung-joon Yang

发明人： Young-ho Lee ,  Seung-joon Yang

IPC分类号： H04N7/01

CPC分类号： H04N7/0115 ,  H04N5/253 ,  H04N19/132 ,  H04N19/427 ,  H04N19/587 ,  H04N19/85

摘要： An image processing device and method to select a field to use in interpolation, if an input image is a film image. The image processing device includes a field selector to select a field to use to interpolate a current field based on difference values in field data among first, second, and third fields being consecutively input in an input image, the field to use to interpolate the current image being one of the first and the third fields and the current field being the second field, a film detector to generate a pattern based on the difference values in the field data between the first, second, and third fields and to determine whether the input image is a film image based on the generated pattern, and an interpolator to interpolate the second field using the one of the first and third field selected by the field selector if the film detector determines the input image to be a film image. Accordingly, when the input image is a film image without a bad-edit, the interpolation process is executed by selecting two temporarily consecutive fields of a field to be interpolated, and using the field with a smaller difference values in field data from the field to be interpolated and a problem of judder in images can be resolved.

摘要翻译： 如果输入图像是胶片图像，则选择要在插值中使用的场的图像处理装置和方法。 图像处理装置包括场选择器，用于基于在输入图像中连续输入的第一，第二和第三场中的场数据中的差值来选择用于内插当前场的场，所述场用于内插当前场 图像是第一和第三场中的一个，当前场是第二场，膜检测器，用于基于第一场，第二场和第三场之间的场数据中的差值生成模式，并确定输入 图像是基于所生成的图案的胶片图像，以及内插器，如果胶片检测器将输入图像确定为胶片图像，则使用场选择器选择的第一和第三场中的一个来内插第二场。 因此，当输入图像是没有不良编辑的胶片图像时，通过选择要插值的场的两个临时连续的场来执行内插处理，并且使用来自场的场数据中具有较小差值的场 被插值，可以解决图像抖动问题。

公开(公告)号：US07499102B2

公开(公告)日：2009-03-03

申请号：US11237975

申请日：2005-09-29

申请人： Young-ho Lee ,  Seung-joon Yang

发明人： Young-ho Lee ,  Seung-joon Yang

IPC分类号： H04N7/01

CPC分类号： H04N7/0115 ,  H04N5/21 ,  H04N7/012 ,  H04N7/0147 ,  H04N21/4884

摘要： An image processing apparatus using a judder-map and a method thereof. The image processing apparatus using a judder-map includes: a field storage block to receive an input interlaced video signal including an input image having a plurality of consecutive fields, a film detecting block to receive the plurality of the consecutive fields from the field storage block and to detect whether the input image is an image in a film mode, a judder-map generating block to detect judder created on a pixel or block of neighboring fields among the plurality of consecutive fields provided from the field storage block to generate a judder-map, and an image interpolating block to perform image interpolation using the judder-map if the input video signal is detected to be an image in the film mode and to generate and output a progressive video signal. The image processing apparatus prevents the creation of judder on CGI (Computer Graphic Imagery) or subtitles, to which pulldown technologies are not applied.

摘要翻译： 一种使用抖动图的图像处理装置及其方法。 使用抖动图的图像处理装置包括：场存储块，用于接收包括具有多个连续场的输入图像的输入隔行视频信号;电影检测块，用于从场存储块接收多个连续场; 并且检测所述输入图像是否是胶片模式中的图像，抖动图生成块，用于检测从所述场存储块提供的所述多个连续字段中的相邻场的像素或块上产生的抖动，以产生抖动 - 地图和图像内插块，以便如果输入视频信号被检测为胶卷模式中的图像并且产生并输出逐行视频信号，则使用抖动图进行图像插值。 图像处理装置防止在不应用下拉技术的CGI（计算机图形图像）或字幕上产生抖动。

公开(公告)号：US07412115B2

公开(公告)日：2008-08-12

申请号：US10962900

申请日：2004-10-13

申请人： Hwa-sup Lim ,  Young-ho Lee

发明人： Hwa-sup Lim ,  Young-ho Lee

IPC分类号： G06K9/32 ,  G06K9/36 ,  G06F17/00

CPC分类号： G06T3/403 ,  G06T3/4007

摘要： An image processing device and a method thereof. The image processing device includes a mapper to map a two-dimensional plane of an input image into a three-dimensional vector surface, a coefficient calculator to calculate a coefficient with respect to an equation of a plane formed by a plurality of pixels mapped by the mapper, and an interpolator to interpolate by calculating a gray-level of a location to be interpolated based on the equation of the plane obtained by the coefficient calculator. When the pixels on the 2-D plane are mapped into the 3-D vector space, the image processing device according to an exemplary embodiment of the present general inventive concept prevents overshoot or undershoot which may occur at the edges or on planes, and thus displays a smooth image.

摘要翻译： 一种图像处理装置及其方法。 图像处理装置包括将输入图像的二维平面映射成三维矢量面的映射器，计算与由多个像素映射的多个像素形成的平面的方程式的系数的系数计算部 映射器和内插器，用于通过基于由系数计算器获得的平面的方程式计算要插值的位置的灰度级来插值。 当2-D平面上的像素被映射到3-D向量空间中时，根据本发明总体构思的示例性实施例的图像处理装置防止可能发生在边缘或平面上的过冲或下冲，因此 显示平滑的图像。