公开(公告)号：USD613883S1

公开(公告)日：2010-04-13

申请号：US29331838

申请日：2009-02-02

申请人： Kenneth Staten ,  Brian Johnson

设计人： Kenneth Staten ,  Brian Johnson

公开(公告)号：US07698499B2

公开(公告)日：2010-04-13

申请号：US11496302

申请日：2006-07-31

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F5/065 ,  G06F5/10 ,  G06F7/725 ,  G06F13/1689 ,  G06F2205/106 ,  H04L49/90 ,  H04L49/901

摘要： A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change the pointer location of the read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

摘要翻译： 一种使用先进先出（FIFO）缓冲器系统在电子设备中缓冲数据流的方法，其中第一读取锁存信号不改变读取指针的指针位置。 还公开了根据本发明的动态随机存取存储器（DRAM）和系统，以包括用于缓冲DRAM内的存储器地址和命令的FIFO缓冲器系统，直到相应的数据可用。

公开(公告)号：US20100036674A1

公开(公告)日：2010-02-11

申请号：US12532376

申请日：2008-03-19

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06Q10/00

CPC分类号： G06Q50/32 ,  G06Q10/08 ,  G06Q10/083 ,  G06Q50/28

摘要： There is provided a system and method for operating an electronic parcel compartment system, whereby at least one user is authorized to deposit a shipment so that the shipment can be forwarded to a logistics service provider. An exemplary method comprises acquiring data about an intended shipment and user data by a first acquisition device separated from the electronic parcel compartment system. The exemplary method also comprises supplementing the shipment information pertaining to the shipment via a second acquisition device located at the electronic parcel compartment system. The exemplary method additionally comprises verifying access rights of the user with a verification device that is arranged within the electronic parcel compartment system, by associating the acquired user data with a stored user profile and verifying validity of the acquired shipment.

摘要翻译： 提供了一种用于操作电子包裹室系统的系统和方法，由此至少一个用户被授权存放货物，使得货物可以转发到物流服务提供商。 一种示例性方法包括通过与电子包裹室系统分离的第一采集装置获取关于预期货物和用户数据的数据。 该示例性方法还包括通过位于电子包裹室系统的第二采集装置补充与装运有关的装运信息。 该示例性方法另外包括通过将所获取的用户数据与存储的用户简档相关联并验证所获取的装运的有效性来验证布置在电子包裹箱系统内的验证装置的用户的访问权限。

公开(公告)号：US07577212B2

公开(公告)日：2009-08-18

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H03K9/00

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US20090067267A1

公开(公告)日：2009-03-12

申请号：US12266397

申请日：2008-11-06

申请人： Christopher S. Johnson ,  Brian Johnson

发明人： Christopher S. Johnson ,  Brian Johnson

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/1087 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

摘要： A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

摘要翻译： 逻辑电路在动态随机存取存储器件中以低功率模式，高写延迟模式或高功率模式，低写延迟模式操作写接收器。 逻辑电路接收指示高功率，低写入等待时间模式是否已经被使能的第一信号，指示存储器装置中的行存储器单元是否有效的第二信号，指示存储器件 正在以断电模式操作，并且指示存储器装置中的读取发送器是否有效的第四信号。 只要存储器件中的一行存储器单元处于活动状态，存储器件没有在掉电模式下运行，则只要高功率，低写入延迟模式被使能，逻辑电路就保持写入接收器的电源， 读存储器中的发送器不起作用。

公开(公告)号：US07499824B2

公开(公告)日：2009-03-03

申请号：US11566107

申请日：2006-12-01

申请人： Brian Johnson ,  John Breyer ,  Joseph Albert Savage

发明人： Brian Johnson ,  John Breyer ,  Joseph Albert Savage

IPC分类号： G06F17/40 ,  G06F11/00

CPC分类号： G06F9/44505 ,  G05B2219/23258 ,  G05B2219/23291 ,  G05B2219/2656 ,  G06F8/71 ,  G06F19/00 ,  H04L41/22 ,  H04L43/50

摘要： System and method for using a graphical user interface (GUI) to generate a measurement task specification (MTS) for performing a measurement task. The measurement task includes measurement and/or signal generation. A measurement task specifier presents a GUI which guides a user in specifying the measurement task. The GUI presents a plurality of GUI elements, e.g., panels, for specifying a plurality of parameters for the measurement task, including measurement type, devices, channels, timing, and/or triggering. The GUI receives user input indicating values for the parameters, and may provide default values for at least some of the parameters. The GUI stores the parameter values in a memory, analyzes the parameter values, and generates the MTS in response to the analyzing. The MTS is then useable to produce a program which implements the measurement task. The specifier may programmatically generate the program, e.g., a graphical program, which is executable to perform the task.

摘要翻译： 用于使用图形用户界面（GUI）生成用于执行测量任务的测量任务规范（MTS）的系统和方法。 测量任务包括测量和/或信号生成。 测量任务说明符呈现指导用户指定测量任务的GUI。 GUI呈现用于指定测量任务的多个参数的多个GUI元件，例如面板，包括测量类型，设备，通道，定时和/或触发。 GUI接收指示参数的值的用户输入，并且可以为至少一些参数提供默认值。 GUI将参数值存储在存储器中，分析参数值，并根据分析生成MTS。 然后，MTS可用于产生实现测量任务的程序。 说明符可以以编程方式生成程序，例如可执行以执行任务的图形程序。

公开(公告)号：US07457172B2

公开(公告)日：2008-11-25

申请号：US11999383

申请日：2007-12-04

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US07371069B2

公开(公告)日：2008-05-13

申请号：US10797232

申请日：2004-03-10

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G09B23/00

CPC分类号： C07D311/94 ,  A61F2/141 ,  A63H3/38 ,  A63H3/42 ,  B29C39/18 ,  B29D11/02 ,  C07C53/23

摘要： Apparatus, methods and articles of manufacture are disclosed for installing an artificial eye in a realistic, life-like sculpture, comprising an artificial eye of partially hemispherical shape, as well as a manikin with an eye-mounting area adapted to mate with such an artificial eye without risk of subsequent movement of the eye or of distortion of the features surrounding the eye-mounting area of the sculpture. Eye mounting pieces for retrofitting existing sculptures having conventional eye mounting areas to permit the accurate and life-like mounting of artificial eyes are also provided.

摘要翻译： 公开的装置，方法和制造方法用于将人造眼睛安装在包括部分半球形的人造眼睛的逼真的，类似生命的雕塑中，以及具有眼睛安装区域的人体模型，适合与这种人造 眼睛没有眼睛后续运动的风险或围绕雕塑的眼睛安装区域的特征变形。 还提供了用于改装具有常规眼睛安装区域的现有雕塑的眼睛安装件，以允许人造眼睛的准确和类似寿命的安装。

公开(公告)号：US07276949B2

公开(公告)日：2007-10-02

申请号：US11349801

申请日：2006-02-08

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： H03H11/16

CPC分类号： G11C7/22 ,  G06F1/06 ,  G11C7/222 ,  H03K5/15013 ,  H03K2005/00286

摘要： A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A third-phase clock signal is generated one and one half clock cycles of the first input clock signal after generating the second-phase clock signal in response to a second input clock signal. A fourth-phase clock signal is generated one clock cycle of the first input clock signal after generating the third-phase clock signal in response to the second input clock signal.

摘要翻译： 响应于第一输入时钟信号产生第一相位时钟信号。 在响应于第一输入时钟信号产生第一相位时钟信号之后，第一输入时钟信号的一个时钟周期产生第二相时钟信号。 响应于第二输入时钟信号产生第二相时钟信号后，第一输入时钟信号的一个半个时钟周期产生第三相时钟信号。 在响应于第二输入时钟信号产生第三相时钟信号之后，第一输入时钟信号的一个时钟周期产生第四相时钟信号。

公开(公告)号：US07254067B2

公开(公告)日：2007-08-07

申请号：US11367468

申请日：2006-03-03

申请人： Christopher S. Johnson ,  Brian Johnson

发明人： Christopher S. Johnson ,  Brian Johnson

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

摘要： A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

摘要翻译： 逻辑电路在动态随机存取存储器件中以低功率模式，高写延迟模式或高功率模式，低写延迟模式操作写接收器。 逻辑电路接收指示高功率，低写入等待时间模式是否已经被使能的第一信号，指示存储器装置中的行存储器单元是否有效的第二信号，指示存储器件 正在以断电模式操作，并且指示存储器装置中的读取发送器是否有效的第四信号。 只要存储器件中的一行存储器单元处于活动状态，存储器件没有在掉电模式下运行，则只要高功率，低写入延迟模式被使能，逻辑电路就保持写入接收器的电源， 读存储器中的发送器不起作用。