公开(公告)号：US09356156B2

公开(公告)日：2016-05-31

申请号：US13902514

申请日：2013-05-24

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66969 ,  H01L21/02063 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2021/775

摘要： A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm2/Vs and a carrier concentration in a range of approximately 1018 cm−3 to approximately 5×1019 cm−3. Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

摘要翻译： 制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。 通过溅射将载流子传输结构沉积在栅极介电层上。 载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。 非晶金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。 源极/漏极触点位于保护层上并与之电接触。

公开(公告)号：US20160056297A1

公开(公告)日：2016-02-25

申请号：US14833462

申请日：2015-08-24

申请人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

发明人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L23/00 ,  H01L29/49

CPC分类号： H01L29/7869 ,  H01L21/321 ,  H01L21/324 ,  H01L21/383 ,  H01L21/428 ,  H01L21/44 ,  H01L21/47635 ,  H01L21/477 ,  H01L21/823418 ,  H01L23/3171 ,  H01L23/564 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

摘要翻译： 一种方法，包括提供具有栅极的衬底，与栅极相邻的栅极绝缘体材料层和位于与栅极相对的栅极绝缘体上的金属氧化物半导体材料层，形成选择性图案化的蚀刻停止钝化层并在高温下加热 在含氧或含氮或惰性气氛中选择性地增加未被蚀刻停止层覆盖的金属氧化物半导体的区域中的载流子浓度，其上形成有上层和间隔开的源极/漏极金属。 随后在含氧或含氮或惰性气氛中加热晶体管，以进一步改善源极/漏极接触并将阈值电压调节到所需的电平。 在晶体管的顶部提供额外的钝化层，具有电气绝缘和对周围环境中的潮湿和化学物质的阻隔性能。

公开(公告)号：US20150303311A1

公开(公告)日：2015-10-22

申请号：US14753460

申请日：2015-06-29

申请人： Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

发明人： Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L23/29 ,  H01L29/423 ,  H01L29/66 ,  H01L23/31

CPC分类号： H01L29/7869 ,  H01L21/02266 ,  H01L21/02269 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02565 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film circuit includes a thin film transistor with a metal oxide semiconductor channel having a conduction band minimum (CBM) with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band minimum (CBM) with a second energy level. The second energy level being lower than, equal to, or no more than 0.5 eV above the first energy level. The circuit is used for an electronic device including any one of an AMLCD, AMOLED, AMLED, AMEPD.

摘要翻译： 薄膜电路包括具有具有第一能级的导带最小（CBM）的金属氧化物半导体沟道的薄膜晶体管。 晶体管还包括覆盖金属氧化物半导体沟道的至少一部分的钝化材料层。 钝化材料具有具有第二能级的导带最小值（CBM）。 第二能量水平低于等于或不超过第一能级的0.5eV。 该电路用于包括AMLCD，AMOLED，AMLED，AMEPD中的任何一种的电子设备。

公开(公告)号：US09129868B2

公开(公告)日：2015-09-08

申请号：US13481781

申请日：2012-05-26

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

IPC分类号： H01L21/00 ,  H01L27/12

CPC分类号： H01L27/1288 ,  H01L27/1225

摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

摘要翻译： 制造具有减小的掩模操作的TFT和IPS的方法包括基板，栅极，栅极上的栅极电介质层和周围的衬底表面以及栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 S / D金属层在通道保护层和暴露的半导体金属氧化物的一部分上被图案化以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层以限定覆盖第一电极的第二IPS电极。

公开(公告)号：US09099563B2

公开(公告)日：2015-08-04

申请号：US14552641

申请日：2014-11-25

申请人： Chan-Long Shieh ,  Gang Yu

发明人： Chan-Long Shieh ,  Gang Yu

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/04 ,  H01L27/12 ,  H01L21/16 ,  H01L21/00

CPC分类号： H01L29/04 ,  H01L21/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/16 ,  H01L21/28556 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L51/5012

摘要： A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

摘要翻译： 薄膜半导体器件具有包括非晶半导体离子金属氧化物和非晶绝缘共价金属氧化物的混合物的半导体层。 一对端子被定位成与半导体层连通并且限定导电通道，并且栅极端子定位成与导电沟道连通并进一步定位成控制沟道的导通。 本发明还包括在沉积过程中沉积包括使用氮气的混合物的方法，以控制所得半导体层中的载流子浓度。

公开(公告)号：US20150115260A1

公开(公告)日：2015-04-30

申请号：US14552641

申请日：2014-11-25

申请人： Chan-Long Shieh ,  Gang Yu

发明人： Chan-Long Shieh ,  Gang Yu

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L29/04 ,  H01L21/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/16 ,  H01L21/28556 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L51/5012

摘要： A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

摘要翻译： 薄膜半导体器件具有包括非晶半导体离子金属氧化物和非晶绝缘共价金属氧化物的混合物的半导体层。 一对端子被定位成与半导体层连通并且限定导电通道，并且栅极端子定位成与导电沟道连通并进一步定位成控制沟道的导通。 本发明还包括在沉积过程中沉积包括使用氮气的混合物的方法，以控制所得半导体层中的载流子浓度。

公开(公告)号：US08679905B2

公开(公告)日：2014-03-25

申请号：US13155749

申请日：2011-06-08

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC分类号： H01L21/84

CPC分类号： H01L29/7869 ,  H01L21/428 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

摘要： A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

摘要翻译： 在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括：提供栅极，栅极电介质，具有带隙的高载流子浓度金属氧化物半导体有源层和间隔开的源/漏极金属接触体 薄膜晶体管配置。 间隔开的源极/漏极金属触点限定有源层中的沟道区。 在沟道区域附近提供氧化环境，并且栅极和沟道区域在氧化环境中被加热以降低沟道区域中的载流子浓度。 或者或另外每个源极/漏极触点包括位于金属氧化物半导体有源层上的非常薄的低功函数金属层，并且高功函数金属的势垒层位于低功函数金属上。

公开(公告)号：US08592817B2

公开(公告)日：2013-11-26

申请号：US13564746

申请日：2012-08-02

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565

摘要： A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.

摘要翻译： 一种在透明基板上制造MOTFT的方法，该方法是将不透明栅极金属定位在衬底前表面上，并沉积覆盖在栅极金属上的栅介质材料以及介电材料上的周围区域和金属氧化物半导体材料。 在半导体材料和蚀刻停止材料上的光致抗蚀剂上沉积选择性可移除的蚀刻停止材料以限定半导体材料中的隔离区域。 去除蚀刻停止件的未覆盖部分。 使用栅极金属作为掩模从基板后表面露出光致抗蚀剂，并去除暴露部分，留下覆盖栅极金属的蚀刻停止材料。 蚀刻半导体材料以隔离TFT。 选择性地蚀刻蚀刻停止层以留下覆盖栅极金属的部分限定沟道区域。 沉积和图案化导电材料以在通道区域的相对侧上形成源区和漏区。

公开(公告)号：US20130143395A1

公开(公告)日：2013-06-06

申请号：US13758293

申请日：2013-02-04

申请人： Chan-Long Shieh ,  Gang Yu

发明人： Chan-Long Shieh ,  Gang Yu

IPC分类号： H01L21/02

CPC分类号： H01L29/04 ,  H01L21/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/16 ,  H01L21/28556 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L51/5012

摘要： A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

公开(公告)号：US20120218241A1

公开(公告)日：2012-08-30

申请号：US13034458

申请日：2011-02-24

申请人： Chan-Long Shieh ,  Gang Yu

发明人： Chan-Long Shieh ,  Gang Yu

IPC分类号： G06F3/038

CPC分类号： G09G3/3225 ,  G09G2310/063 ,  G09G2320/0204

摘要： A method of driving a display device includes providing an array of pixels including rows and columns of pixels, each pixel including a switching/driving transistor circuit and at least one light emitting device. Each row of pixels has a scan line and each column of pixels has a data line. The method further includes defining a frame period during which each pixel in the array of pixels is addressed and dividing the frame period into a write subframe, a display subframe, and a rest subframe. A scan pulse is supplied to each scan line, a data signal to each data line and the light emitting devices are disabled during the write subframe. The light emitting devices are enabled during the display subframe and the switching/driving transistor circuits are disabled. A rest pulse is supplied to all scan lines and the light emitting devices are disabled during the rest subframe.

摘要翻译： 一种驱动显示装置的方法包括提供包括行和列的像素的像素阵列，每个像素包括开关/驱动晶体管电路和至少一个发光器件。 每行像素具有扫描线，并且每列像素具有数据线。 该方法还包括定义帧期间，在该帧周期期间，像素阵列中的每个像素被寻址并且将帧周期划分为写子帧，显示子帧和剩余子帧。 向每条扫描线提供扫描脉冲，在写入子帧期间，对每个数据线的数据信号和发光器件禁用。 发光器件在显示子帧期间被使能，并且开关/驱动晶体管电路被禁止。 向所有扫描线提供静止脉冲，并且在其余子帧期间禁用发光装置。