Abstract:
According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.
Abstract:
Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter in a nested manner. The dithering algorithm may be modified to immediately check the MSE after a parameter has been adjusted.
Abstract:
Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.
Abstract:
An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.
Abstract:
High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.
Abstract:
An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.
Abstract:
Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter. The dithering algorithm may include a state machine to alter the rate of change dependent on the state of the dithering algorithm.
Abstract:
A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.
Abstract:
High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.
Abstract:
Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.