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    DOUBLE GATED THIN FILM TRANSISTORS
    113.
    发明申请
    DOUBLE GATED THIN FILM TRANSISTORS 审中-公开

    公开(公告)号：US20200006573A1

    公开(公告)日：2020-01-02

    申请号：US16022480

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Gilbert DEWEY ,  Willy RACHMADY

    IPC: H01L29/786 ,  H01L29/423

    Abstract: Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS
    114.
    发明申请
    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS 审中-公开

    公开(公告)号：US20200006388A1

    公开(公告)日：2020-01-02

    申请号：US16024696

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

    IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

    STACKED THIN FILM TRANSISTORS
    115.
    发明申请
    STACKED THIN FILM TRANSISTORS 审中-公开

    公开(公告)号：US20190393249A1

    公开(公告)日：2019-12-26

    申请号：US16016387

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

    IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN
    118.
    发明申请
    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN 审中-公开

    公开(公告)号：US20190172941A1

    公开(公告)日：2019-06-06

    申请号：US16304620

    申请日：2016-07-02

    Applicant: INTEL CORPORATION

    Inventor： Willy RACHMADY ,  Sanaz K. GARDNER ,  Chandra S. MOHAPATRA ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

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