公开(公告)号：US10356197B2

公开(公告)日：2019-07-16

申请号：US15414036

申请日：2017-01-24

Applicant: Intel Corporation

Inventor： Vallabhajosyula S. Somayazulu ,  Eve M. Schooler ,  Hassnaa Moustafa ,  Andrew Stephen Brown ,  Rath Vannithamby ,  Srikathyayani Srikanteswara ,  David John Zage ,  Ren Wang ,  Christian Maciocco ,  David E. Ott ,  Jeffrey C. Sedayao ,  David E. Cohen ,  Sung Lee

IPC: H04L29/08 ,  H04L12/26 ,  H04L29/06 ,  G06F16/23 ,  H04L12/841 ,  H04L12/773 ,  H04L12/741 ,  H04L12/813 ,  H04L12/24 ,  H04L29/12 ,  H04L12/721 ,  H04L12/911 ,  H04L12/715 ,  G06F16/957 ,  H04W56/00 ,  H04W4/02 ,  G06F3/14 ,  G06F3/0481 ,  G06F3/0482

Abstract: Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.

公开(公告)号：US20190102301A1

公开(公告)日：2019-04-04

申请号：US15720379

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bin Li ,  Chunhui Zhang ,  Ren Wang ,  Ram Huggahalli

IPC: G06F12/0831 ,  G06F9/30 ,  G06F9/46 ,  H04L12/741 ,  H04L12/933

Abstract: Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which is configured to receive a network packet, write the payload of the network packet to a data storage device of the target computing device, and obtain, subsequent to having transmitted a last write request to write the payload to the data storage device, ownership of a flag cache line of a cache of the target computing device. The NIC is additionally configured to receive a snoop request from a processor of the target computing device, identify whether the received snoop request corresponds to a read flag snoop request associated with an active request being processed by the NIC, and hold the received snoop request for delayed return in response to having identified the received snoop request as the read flag snoop request. Other embodiments are described herein.

公开(公告)号：US20190052719A1

公开(公告)日：2019-02-14

申请号：US15862311

申请日：2018-01-04

Applicant: Intel Corporation

Inventor： Yipeng Wang ,  Ren Wang ,  Antonio Fischetti ,  Sameh Gobriel ,  Tsung-Yuan C. Tai

IPC: H04L29/08 ,  H04L12/24 ,  H04L29/06

Abstract: Technologies for flow rule aware exact match cache compression include multiple computing devices in communication over a network. A computing device reads a network packet from a network port and extracts one or more key fields from the packet to generate a lookup key. The key fields are identified by a key field specification of an exact match flow cache. The computing device may dynamically configure the key field specification based on an active flow rule set. The computing device may compress the key field specification to match a union of non-wildcard fields of the active flow rule set. The computing device may expand the key field specification in response to insertion of a new flow rule. The computing device looks up the lookup key in the exact match flow cache and, if a match is found, applies the corresponding action. Other embodiments are described and claimed.

公开(公告)号：US20190044869A1

公开(公告)日：2019-02-07

申请号：US15999133

申请日：2018-08-17

Applicant: Intel Corporation

Inventor： Yipeng Wang ,  Ren Wang ,  Janet Tseng ,  Jr-Shian Tsai ,  Tsung-Yuan Tai

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/713 ,  H04L12/26 ,  H04L29/08 ,  G06F11/34

Abstract: Technologies for classifying network flows using adaptive virtual routing include a network appliance with one or more processors. The network appliance is configured to identify a set of candidate classification algorithms from a plurality of classification algorithm designs to perform a flow classification operation and deploy each of the candidate classification algorithms to a processor. Additionally the network appliance is configured to monitor a performance level of each of the deployed candidate classification algorithms and identify a candidate classification algorithm of the deployed candidate classification algorithms with the highest performance level. The network appliance is further configured to deploy the identified candidate classification algorithm with the highest performance level on each of the one or more processors that are configured to perform the flow classification operation. Other embodiments are described herein.

公开(公告)号：US20190042388A1

公开(公告)日：2019-02-07

申请号：US16022543

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Ren Wang ,  Bin Li ,  Andrew J. Herdrich ,  Tsung-Yuan C. Tai ,  Ramakrishna Huggahalli

IPC: G06F11/34 ,  G06F12/0811 ,  G06F12/121 ,  G06F13/16 ,  G06F13/42 ,  G06F11/30

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

公开(公告)号：US20190004970A1

公开(公告)日：2019-01-03

申请号：US15636235

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Binh Q. Pham ,  Ren Wang

IPC: G06F12/128 ,  G06F12/0897 ,  G06F12/0891 ,  G06F3/06

Abstract: Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.

公开(公告)号：US20180157591A1

公开(公告)日：2018-06-07

申请号：US15369594

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Ren Wang ,  Namakkal N. Venkatesan ,  Patrick Lu

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected information to the cache, and a prefetch tuning buffer including tuning state for the set of candidate prefetcher algorithms, wherein the prefetcher is to adjust operation of the prefetcher algorithm based on the tuning state.

公开(公告)号：US09992299B2

公开(公告)日：2018-06-05

申请号：US15426718

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/741 ,  H04L12/721 ,  H04L12/743

CPC classification number: H04L67/2852 ,  H04L41/0893 ,  H04L45/38 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/00

Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.

公开(公告)号：US09829949B2

公开(公告)日：2017-11-28

申请号：US14126884

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Alexander W. Min ,  Ren Wang ,  Jr-Shian Tsai ,  Mesut A. Ergin ,  Tsung-Yuan C. Tai

IPC: G06F13/24 ,  G06F1/32 ,  H04L12/12 ,  H04L12/861

CPC classification number: G06F1/32 ,  G06F1/3209 ,  G06F1/3278 ,  G06F1/329 ,  G06F13/24 ,  H04L12/12 ,  H04L49/90 ,  H04L49/9063 ,  Y02D10/157 ,  Y02D10/24 ,  Y02D50/40

Abstract: Methods and apparatus relating to adaptive interrupt coalescing for energy efficient mobile platforms are discussed herein. In one embodiment, one or more interrupts are buffered based on communication throughput. At least one of the one or more interrupts are released in response to expiration of an interrupt coalescing time period. Other embodiments are also claimed and described.

公开(公告)号：US20170286114A1

公开(公告)日：2017-10-05

申请号：US15089533

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Yipeng Wang ,  Ren Wang ,  Tsung-Yuan Charles Tai ,  Jr-Shian Tsai

IPC: G06F9/30 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3824 ,  G06F9/3836 ,  G06F12/0804 ,  G06F12/0862 ,  G06F2212/6028

Abstract: A processor of an aspect includes a decode unit to decode memory access instructions of a first type and to output corresponding memory access operations, and to decode memory access instructions of a second type and to output corresponding memory access operations. The processor also includes a load store queue coupled with the decode unit. The load store queue includes a load buffer that is to have a plurality of load buffer entries, and a store buffer that is to have a plurality of store buffer entries. The load store queue also includes a buffer entry allocation controller coupled with the load buffer and coupled with the store buffer. The buffer entry allocation controller is to allocate load and store buffer entries based at least in part on whether memory access operations correspond to memory access instructions of the first type or of the second type. Other processors, methods, and systems, are also disclosed.