公开(公告)号：US06757415B1

公开(公告)日：2004-06-29

申请号：US10461301

申请日：2003-06-13

申请人： Steven K. Rogers ,  Kenneth W. Bauer ,  Michael J. Collins ,  Martin P. DeSimio ,  Richard A. Mitchell

发明人： Steven K. Rogers ,  Kenneth W. Bauer ,  Michael J. Collins ,  Martin P. DeSimio ,  Richard A. Mitchell

IPC分类号： G06K900

CPC分类号： G06K9/6293 ,  G06K9/4609 ,  G06K9/56 ,  G06K2209/05 ,  G06T7/0012 ,  G06T2207/30068

摘要： A computer aided detection method and system to assist radiologists in the reading of medical images. The method and system has particular application to the area of mammography including detection of clustered microcalcifications and densities. A microcalcification detector is provided wherein individual detections are rank ordered and classified, and one of the features for classification is derived using a multilayer perceptron. A density detector is provided including an iterative, dynamic region growing module with embedded subsystem for rank ordering and classification of a best subset of candidate masks. Features are computed from a detection on an input image by providing first and second regions on the input image corresponding to areas inside and outside the detection, measurements are computed based on values derived from the two regions, a standard deviation is computed for the measurements in each region, and a feature for the detection is computed using a Bauer-Fisher ratio. A post processing stage is provided where detections are analyzed in the context of a set of images for a patient. The final output of the system is a set of indications overlaid on the input medical images.

摘要翻译： 一种计算机辅助检测方法和系统，用于帮助放射科医师阅读医学图像。 该方法和系统在乳腺摄影领域具有特殊应用，包括检测聚类微钙化和密度。 提供了一种微钙化检测器，其中单独的检测是排序和分类的，并且使用多层感知器导出用于分类的特征之一。 提供了一种密度检测器，其包括具有嵌入式子系统的迭代动态区域增长模块，用于对候选掩模的最佳子集进行排序和分类。 通过在对应于检测内部和外部的区域的输入图像上提供第一和第二区域来对输入图像上的检测计算特征，根据从两个区域导出的值来计算测量值，计算标准偏差 每个区域和用于检测的特征使用鲍尔 - 费雪比来计算。 提供后处理阶段，其中在用于患者的一组图像的上下文中分析检测。 系统的最终输出是覆盖在输入医学图像上的一组指示。

公开(公告)号：US06272651B1

公开(公告)日：2001-08-07

申请号：US09135274

申请日：1998-08-17

申请人： Kenneth T. Chin ,  Clarence Kevin Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert Allen Lester ,  Gary J. Piccirillo

发明人： Kenneth T. Chin ,  Clarence Kevin Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert Allen Lester ,  Gary J. Piccirillo

IPC分类号： G06F1100

CPC分类号： G06F11/10

摘要： A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads. If the read request is from a device on a peripheral bus (AGP or PCI bus), then the system interface unit performs the data integrity protocol on the data and error bits before forwarding the read data to the appropriate bus.

摘要翻译： 提供了一种具有耦合在主存储器，CPU总线以及PCI总线和/或图形总线之间的系统接口单元的计算机。 硬盘驱动器通常耦合到PCI总线。 系统接口单元被配置为执行数据完整性协议。 此外，处理器总线上的所有总线主控器件（CPU）可以执行相同的数据完整性协议。 当CPU从主存储器请求读取数据时，总线接口单元将未修改的读取数据和错误信息转发到绕过系统接口单元内的数据完整性逻辑的处理器总线。 然而，系统接口单元仍然可以与请求CPU并行地执行数据完整性协议，使得系统接口单元可以跟踪错误并且可能通知操作系统或其他错误控制软件的任何错误。 以这种方式，处理器读取延迟得到改善而不牺牲数据完整性。 此外，系统接口单元仍然可以跟踪处理器读取的错误。 如果读取请求来自外围总线（AGP或PCI总线）上的设备，则系统接口单元在将读取的数据转发到适当的总线之前对数据和错误位执行数据完整性协议。

公开(公告)号：US06216190B1

公开(公告)日：2001-04-10

申请号：US09164192

申请日：1998-09-30

申请人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

发明人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

IPC分类号： G06F1342

CPC分类号： G06F13/4239

摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the peripheral bus and memory bus. Those cycles can be arranged in order within the CPU bus pipeline. A subset of cycles destined for a peripheral bus can be stalled within a snoop phase associated with the CPU bus. Snoop stall can continue until a memory cycle is encountered upon the CPU bus pipeline within a phase prior to the snoop phase. Once the memory cycle progresses to the snoop phase, snoop stall can be discontinued and the previous, peripheral cycles can then be deferred and/or retried, allowing the memory cycle to be quickly dispatched through all phases of the CPU bus and onto the memory bus. In this fashion, memory cycles can be completed quickly, yet deferrals or retries are minimized to avoid the throughput penalty associated with deferring or retrying cycles back again through each phase of the CPU bus.

摘要翻译： 提供一种具有耦合在CPU总线，外围总线和存储器总线之间的总线接口单元的计算机。 总线接口单元包括连接到CPU总线的处理器控制器，用于控制从CPU到外围总线和存储器总线的周期传送。 这些循环可以顺序排列在CPU总线管道中。 在与CPU总线相关联的窥探阶段中，可能会停止发往外围总线的周期的子集。 在窥探阶段之前的一个阶段，在CPU总线流水线上，Snoop停止可以继续，直到遇到内存循环。 一旦存储器周期进行到窥探阶段，就可以停止侦听停止，然后可以延迟和/或重试先前的周边周期，从而允许通过CPU总线的所有阶段和存储器总线快速调度存储器周期 。 以这种方式，可以快速完成内存周期，但是延迟或重试最小化，以避免通过CPU总线的每个阶段再次延迟或重试周期相关的吞吐量损失。

公开(公告)号：US06209052B1

公开(公告)日：2001-03-27

申请号：US09164194

申请日：1998-09-30

申请人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

发明人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

IPC分类号： G06F1300

CPC分类号： G06F13/1605 ,  G06F13/4243

摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.

摘要翻译： 提供一种计算机，其具有耦合在CPU总线，外围总线（即PCI总线和/或图形总线）之间的总线接口单元和存储器总线。 总线接口单元包括链接到相应总线的控制器，以及放置在各种控制器之间的地址和数据路径内的多个队列。 外设总线控制器可以将写周期解码为存储器，然后处理器控制器可以请求并授予CPU本地总线的所有权。 然后可以窥探写周期的地址，以确定CPU高速缓存存储位置中是否存在有效数据。 如果是这样，可以进行回写操作。 CPU总线的所有权在侦听操作期间由总线接口单元维护，以及通过外设来源的写周期在写回和存储器总线的请求期间保持。 直到存储器总线的所有权由总线接口单元终止主存的存储器仲裁器才被授予。 因此，总线接口单元将CPU派生的周期从CPU总线保持，以确保存储器仲裁器将所有权授予来自外设总线的写周期。 以这种方式，通过CPU读取周期访问该数据之前，来自外围总线的数据可以存储在系统存储器中。 总线接口单元可以启动的窥探周期数由计算机上电，复位或启动时编程的配置寄存器决定。

公开(公告)号：US06202101B1

公开(公告)日：2001-03-13

申请号：US09164189

申请日：1998-09-30

申请人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

发明人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.

摘要翻译： 提供了一种具有耦合在处理器总线，外围总线和存储器总线之间的总线接口单元的计算机。 总线接口单元包括链接到处理器总线的处理器控制器，用于控制从处理器到外围总线和存储器总线的周期传送。 这些周期最初作为请求转发，由此处理器控制器包括与外围设备请求队列分开的存储器请求队列。 来自存储器和外围设备请求队列的请求可以同时排队到存储器和外围总线。 这增强了读写请求的吞吐量; 但是，必须确保作为读请求返回的数据的正确排序和作为写请求结果传送的数据。 在处理器控制器中还存在按顺序队列，该处理器控制器从周边和存储器请求队列记录请求被分派到外围设备和存储器总线的顺序。 可以根据请求队列中的当前指针位置重新排序并将其显示给目的地。 因此，按顺序队列跟踪数据在整个处理器总线上传输的顺序，与先前请求传送的顺序一致。

公开(公告)号：US5938739A

公开(公告)日：1999-08-17

申请号：US811587

申请日：1997-03-05

申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

公开(公告)号：US5835948A

公开(公告)日：1998-11-10

申请号：US324016

申请日：1994-10-14

申请人： Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

发明人： Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

IPC分类号： G06F12/08

CPC分类号： G06F12/0879 ,  G06F12/0859

摘要： In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.

摘要翻译： 在实现高速缓冲存储器的微计算机系统中，在单行存储器中实现多路高速缓存。 代替使用芯片输出，可以在多路缓存的每种方式的单独物理芯片上实现，单个存储器的地址线用于在各种方式之间进行选择。 以这种方式，可以使用更少的部件，并且单行存储器可以用于多路缓存。

公开(公告)号：US5778413A

公开(公告)日：1998-07-07

申请号：US606546

申请日：1996-02-26

申请人： Jeffrey C. Stevens ,  John E. Larson ,  Gary W. Thome ,  Michael J. Collins ,  Michael Moriarty

发明人： Jeffrey C. Stevens ,  John E. Larson ,  Gary W. Thome ,  Michael J. Collins ,  Michael Moriarty

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/00 ,  G06F13/10

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the Peripheral Component Interconnect (PCI) to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作到存储器队列的外围组件互连（PCI）。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规动态随机存取存储器周期的特定部分的时钟周期数。

公开(公告)号：US5730776A

公开(公告)日：1998-03-24

申请号：US607754

申请日：1996-02-27

申请人： Michael J. Collins ,  Donald K. Kofluk

发明人： Michael J. Collins ,  Donald K. Kofluk

IPC分类号： C22B15/00 ,  C22B3/08

CPC分类号： C22B15/0071 ,  Y02P10/236

摘要： There is provided a novel hydrometallurgical process for the extraction of copper from sulphidic concentrates involving an oxidizing pressure leach using dilute sulphuric acid and a carbonaceous additive. The leaching step is carried out preferably at temperatures above the melting point of sulphur but below about 200.degree. C.

摘要翻译： 提供了一种新的湿法冶金方法，用于使用稀硫酸和含碳添加剂从涉及氧化压力浸出的硫化物浓缩物中提取铜。 浸出步骤优选在高于硫的熔点但低于约200℃的温度下进行。

公开(公告)号：US5651947A

公开(公告)日：1997-07-29

申请号：US553175

申请日：1995-11-07

申请人： Michael J. Collins ,  Donald K. Kofluk

发明人： Michael J. Collins ,  Donald K. Kofluk

IPC分类号： C22B3/04 ,  C01G5/00 ,  C01G9/00 ,  C01G21/00 ,  C22B20060101 ,  C22B3/08 ,  C22B19/00 ,  C22B19/20 ,  C22B3/00

CPC分类号： C22B13/04 ,  C22B19/22 ,  C22B3/08 ,  Y02P10/234

摘要： There is provided a novel class of additives, specifically coals, which are useful in zinc extraction processes involving one or more pressure leach stages carried out at temperatures above the melting point of sulphur. Such processes may include those incorporating a single stage pressure leach, a process involving two stage countercurrent or cocurrent pressure leaches or a multistage leach process for recovering zinc, lead and silver from zinc bearing sulphidic materials which also contain lead and silver.

摘要翻译： 提供了一类新的添加剂，特别是煤，其可用于锌提取过程，其涉及在高于硫的熔点的温度下进行的一个或多个压力浸出阶段。 这些方法可以包括那些结合单级压力浸出，涉及两级逆流或并流压力浸出的方法，或用于从含有铅和银的含锌硫化物材料中回收锌，铅和银的多级浸出方法。