-
111.发明申请TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN 失效在设计，合成和物理设计期间减少噪声的转换平衡/ di / dt减少公开(公告)号：US20080043890A1
公开(公告)日：2008-02-21
申请号：US11460065
申请日：2006-07-26
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。
-
公开(公告)号：US07331021B2
公开(公告)日：2008-02-12
申请号：US11163750
申请日：2005-10-28
IPC分类号： G06F17/50
CPC分类号： H03K3/037
摘要： A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.
摘要翻译： 提供了一种快速/慢速状态机锁存器，为单个切换低功率多路复用器电路产生快速和慢速选择信号。 根据本发明的实施例，快速/慢速状态机锁存器包括具有延迟输出的第一锁存器，具有未延迟输出的第二锁存器，用于将第一锁存器的延迟输出耦合到第一锁存器的输入端的反相器 第二锁存器和耦合到第一锁存器的延迟输出的异或（XOR）门和数据输入，XOR门的输出耦合到第一锁存器的输入。 还提供了一种将低功率多路复用器电路并入到具有来自电路设计器的最小输入的电路设计中的方法。
-
113.发明授权System and method for fencing any one of the plurality of voltage islands using a lookup table including AC and DC components for each functional block of the voltage islands 失效用于使用包括用于电压岛的每个功能块的AC和DC分量的查找表来围绕多个电压岛中的任一个的栅栏的系统和方法公开(公告)号：US07275164B2
公开(公告)日：2007-09-25
申请号：US10906017
申请日：2005-01-31
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3296 , Y02D10/171 , Y02D10/172
摘要： An integrated circuit (IC) chip (100) containing a plurality of voltage islands (124I-M) containing corresponding functional blocks (104I-M) that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch (140I-M) and state-saving circuitry (148I-M) for saving the state of the inputs to that functional block. A power modulation unit (PMU) (132) generates fencing signals (144I-M) that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.
摘要翻译： 一种集成电路（IC）芯片（100），其包含多个电压岛（124MIM），其包含相应的功能块（104IM），所述多个电压岛可被有选择地围栏，即断电，同时节省相应的输入的状态， 以便管理芯片的功耗。 每个可变功能块包括用于将输入状态保存到该功能块的电源开关（140I-M）和状态保存电路（148I-M）。 功率调制单元（PMU）（132）产生控制电源开关和省电电路的栅栏信号（144I-M），以选择性地围绕对应的功能块。 PMU根据一个或多个操作参数生成围栏信号。
-
114.发明授权System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit 失效通过分配对DMA机器的固定优先级和对处理单元的可编程优先级来分配存储器分配带宽的系统和方法公开(公告)号：US07213084B2
公开(公告)日：2007-05-01
申请号：US10605591
申请日：2003-10-10
CPC分类号： G06F13/28
摘要： In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了用于分配存储器带宽的第一方法。 第一种方法包括以下步骤：（1）将对存储器带宽的访问的固定优先级分配给一个或多个直接存储器访问（DMA）机器; 以及（2）将对所述存储器带宽的访问的可编程优先级分配给处理单元。 处理单元的可编程优先级允许在一个或多个DMA机器和处理单元之间进行动态调整的优先级分配。 提供了许多其他方面。
-
公开(公告)号：US07107469B2
公开(公告)日：2006-09-12
申请号：US10604328
申请日：2003-07-11
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。
-
公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译： 一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。 本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。 以这种方式，可以为给定期望的阶段提供最佳电压。
-
117.发明授权System and method for inserting leakage reduction control in logic circuits 有权用于在逻辑电路中插入泄漏减少控制的系统和方法公开(公告)号：US06687883B2
公开(公告)日：2004-02-03
申请号：US09750969
申请日：2000-12-28
IPC分类号： G06F1750
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152 , Y02D50/20
摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
摘要翻译： 一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。
-
118.发明授权Method and apparatus for preventing thermal failure in a semiconductor device through redundancy 失效通过冗余来防止半导体器件的热故障的方法和装置公开(公告)号：US06425092B1
公开(公告)日：2002-07-23
申请号：US09098571
申请日：1998-06-17
IPC分类号： G06F1100
CPC分类号： G06F1/206
摘要： Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.
摘要翻译： 备用的冗余芯片部分代替基于某些传感器信号处于过热风险的芯片部分。 当这些信号被接收到处于危险中的芯片部分的操作被传送到冗余芯片部分并且处于危险中的芯片部分被关闭时。 在原始芯片部分冷却后，它可以作为替代芯片部分自身使用。 传感器信号可以基于温度值，经过的操作时间以及芯片部分内的操作数量或速率。
-
公开(公告)号：US06282144B1
公开(公告)日：2001-08-28
申请号：US09524661
申请日：2000-03-13
IPC分类号： G11C800
CPC分类号： G06F13/1684 , G11C8/16
摘要： A multi-port memory is provided that includes means for receiving synchronous memory requests, means for receiving asynchronous memory requests, and means for processing the received synchronous and asynchronous memory requests simultaneously. Systems and methods that employ the multi-port memory are also provided.
摘要翻译： 提供了一种多端口存储器，其包括用于接收同步存储器请求的装置，用于接收异步存储器请求的装置，以及用于同时处理所接收的同步和异步存储器请求的装置。 还提供了使用多端口存储器的系统和方法。
-
120.发明授权公开(公告)号：US06275968B1
公开(公告)日：2001-08-14
申请号：US09129921
申请日：1998-08-06
IPC分类号： G06F1750
CPC分类号： G06F1/32 , G06F1/04 , G06F17/505
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.
摘要翻译： 根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。 优选实施例减少了通常在许多类型的逻辑电路中发生的不必要的切换。 优选实施例通过将设备的一部分保持在先前输出来减少电路中的不需要的节点切换，直到所有输入在每个时钟周期内稳定到其最终值。 这减少了由于不必要的节点切换而通常发生的设备中的功耗。
-
-
-
-
-
-
-
-
-
搜索结果
216 条记录 (耗时 0.028 秒)
