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公开(公告)号：US06282144B1
公开(公告)日：2001-08-28
申请号：US09524661
申请日：2000-03-13
IPC分类号： G11C800
CPC分类号： G06F13/1684 , G11C8/16
摘要： A multi-port memory is provided that includes means for receiving synchronous memory requests, means for receiving asynchronous memory requests, and means for processing the received synchronous and asynchronous memory requests simultaneously. Systems and methods that employ the multi-port memory are also provided.
摘要翻译： 提供了一种多端口存储器，其包括用于接收同步存储器请求的装置，用于接收异步存储器请求的装置，以及用于同时处理所接收的同步和异步存储器请求的装置。 还提供了使用多端口存储器的系统和方法。
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公开(公告)号：US06430073B1
公开(公告)日：2002-08-06
申请号：US09730673
申请日：2000-12-06
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.
摘要翻译： 动态内容可寻址存储器（DCAM）单元拓扑，其包含较少的可以执行不会延迟或中断CAM搜索周期的存储数据的“隐藏”刷新，从而提供类似SCAM的性能。 执行非破坏性读取操作，使得由于刷新读取操作而不必将所存储的数据写回。 可以在读取操作之后，甚至在刷新数据被写回之前执行可靠的CAM搜索。 可以在更新周期的未决期间对每个CAM条目执行软错误检测处理。 DCAM单元可用于数字系统，如数字计算机和网络路由器。
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公开(公告)号：US07117400B2
公开(公告)日：2006-10-03
申请号：US10065723
申请日：2002-11-13
IPC分类号： G06F11/20 , G11C11/4094 , G11C15/00 , G11C15/04
CPC分类号： G11C29/832 , G11C15/00 , G11C29/848
摘要： An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
摘要翻译： 一种集成电路，包括：一组位线; 一组数据线; 用于基于转向信号将每个相应数据线耦合到第一相应位线或第二相应位线的装置，所述第二相应位线与所述第一相应位线相邻; 以及用于在数据线耦合到第二位线之后将第一相应位线保持在期望电位的装置。
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4.发明授权Using one memory to supply addresses to an associated memory during testing 失效在测试期间使用一个内存来提供地址给相关的内存
公开(公告)号：US5563833A
公开(公告)日：1996-10-08
申请号：US398465
申请日：1995-03-03
申请人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
发明人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56 , G11C7/00
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.
摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。
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公开(公告)号：US07562267B2
公开(公告)日：2009-07-14
申请号：US11023677
申请日：2004-12-28
IPC分类号： G01R31/28
CPC分类号： G11C29/32 , G11C29/16 , G11C2029/3202
摘要： In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种第一方法，其包括以下步骤：（1）经由第一信号路径将表示测试操作的第一信号从测试电路发送到存储器; （2）经由第二信号路径将与第一信号同步的第二信号从测试电路发送到存储器; 和（3）响应于到达存储器的第二信号，在存储器上启动测试操作。 提供了许多其他方面。
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公开(公告)号：US07003704B2
公开(公告)日：2006-02-21
申请号：US10292359
申请日：2002-11-12
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/72
摘要： A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.
摘要翻译： 一种用于测试集成电路中的存储器的系统和方法，该集成电路实现BIST测试，以计算行和列冗余，并可以更换有缺陷的行或列的存储单元。 该系统包括用于检测一行中的第一单个存储器单元故障的电路; 并记录第一单节故障（SCF）的I / O值。 提供电路，用于检测测试行是否发生多于一个单电池故障，并且响应于检测到第二SCF，将后续测试行的记录I / O值与与 第一个失败的内存单元。 在检测到有缺陷的位时，替换具有相应的缺陷位的存储器的缺陷列和行。
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公开(公告)号：US5535164A
公开(公告)日：1996-07-09
申请号：US398468
申请日：1995-03-03
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G11C7/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to "ignore" such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory, and capture error information for that particular memory. Hence, a single BIST can be used to test a multiplicity of memories of different sizes and different types.
摘要翻译： 本发明提供了一种可以通过使用状态机来选择和产生测试芯片上所有存储器所需的所有模式并且打印所有数据的不同尺寸，类型和特性的各种存储器，包括 预期数据和所有存储器的地址信息。 BIST还为各种存储器生成独特的（单独的）控制信号，并将这些控制信号印在各种存储器上。 BIST选择性地断言各种控制信号，以便仅对从其唯一控制被断言的那些存储器应用（写入）数据和仅读取和捕获（加载结果）故障信息。 存储器的写入使能信号的选择性断言防止对可能潜在地屏蔽单元写入和泄露缺陷的位置的多次写入，而只有在预期有效的存储器输出数据时执行存储器的负载结果信号的选择性断言，以便不捕获虚假错误信息 。 控制信号指示不使用特定输入序列或给定输入序列的任何部分的那些存储器“忽略”这样的信号，由此产生必要的信号以形成每个存储器的测试图案，数据和 这些模式的地址信息，用于写入和读取每个存储器的控制信号，以及捕获该特定存储器的错误信息。 因此，可以使用单个BIST来测试不同大小和不同类型的多个存储器。
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8.发明授权Memory array built-in self test circuit for testing multi-port memory arrays 失效内存阵列内置自检电路，用于测试多端口存储器阵列
公开(公告)号：US5796745A
公开(公告)日：1998-08-18
申请号：US684519
申请日：1996-07-19
CPC分类号： G11C29/20
摘要： A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-port memory array, a plurality of single-port memory arrays, or a combination thereof by providing unique read/write sequences to the same or to adjacent memory locations.
摘要翻译： 公开了一种内存自检（ABIST）电路，用于测试多端口存储器阵列。 用于ABIST电路的可编程模式发生器允许在多端口存储器阵列中的相同或相邻地址位置处执行不同的R / W数据操作。 可编程模式生成器包括数据发生器，读/写控制器和地址计数器，每个具有与多端口存储器阵列的端口相同数量的输出。 可编程模式发生器还包括频率控制器。 数据发生器用存储器阵列的适当数据模式进行编程，读/写控制器用适当的存储器阵列读/写模式进行编程。 地址计数器是在多端口阵列的每个端口上提供相同或不同的地址，并且频率控制器用适当的频率信息编程，以确定存储器阵列中每个单元的读/写操作的数量。 可编程数据，可编程读/写序列，可编程地址计数器和可编程频率的组合允许通过提供唯一的读/写来对多端口存储器阵列，多个单端口存储器阵列或其组合进行确定性测试 序列到相同或相邻的存储器位置。
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9.发明授权Apparatus and method for real time data error capture and compression redundancy analysis 失效用于实时数据错误捕获和压缩冗余分析的装置和方法
公开(公告)号：US5317573A
公开(公告)日：1994-05-31
申请号：US839678
申请日：1992-02-24
申请人： Orest Bula , Garrett S. Koch , Justin A. Woyke , Richard S. Gomez
发明人： Orest Bula , Garrett S. Koch , Justin A. Woyke , Richard S. Gomez
CPC分类号： G11C29/72 , G11C29/56 , G01R31/31935 , G06F11/2205
摘要： Fail information from testing of a DUT memory array is captured and compressed by utilizing a compression matrix which is related in size to the available redundancy associated with the DUT (device under test) memory array, and which, in essence, defines the limits of redundancy repair. The compression matrix includes a plurality of matrix cells fewer in number than the number of memory cells in the DUT memory array and is arranged in a matrix of compression rows and compression columns, the number R of compression rows in the compression matrix being equal to (a predetermined number of redundant rows in the memory array) times (a predetermined number of redundant memory columns+1), and the number C of compression columns in the compression matrix being equal to (a predetermined number of redundant memory columns) times (a predetermined number of redundant memory rows+1). The compression matrix is loaded with the fail information concurrently with testing of the DUT memory array.
摘要翻译： 通过利用与DUT（被测设备）存储器阵列相关联的可用冗余大小相关的压缩矩阵来捕获和压缩来自测试DUT存储器阵列的故障信息，并且其实质上限定了冗余限制 修理。 压缩矩阵包括多个矩阵单元，其数量少于DUT存储器阵列中的存储器单元的数量，并且被排列成压缩行和压缩列的矩阵，压缩矩阵中的压缩行数R等于 存储器阵列中的预定数量的冗余行）乘以（预定数量的冗余存储器列+ 1），并且压缩矩阵中的压缩列数C等于（预定数量的冗余存储器列）次（a 预定数量的冗余存储器行+ 1）。 压缩矩阵与DUT存储器阵列的测试同时加载失败信息。
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公开(公告)号：US5093584A
公开(公告)日：1992-03-03
申请号：US681626
申请日：1991-05-06
申请人： Justin A. Woyke , Orest Bula , Garrett S. Koch , Richard S. Gomez
发明人： Justin A. Woyke , Orest Bula , Garrett S. Koch , Richard S. Gomez
CPC分类号： H03L7/00 , H03K5/133 , H03K2005/00065 , H03K2005/00104 , H03K2005/00195
摘要： A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. Preferably this ratio circuit comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. An element for discharging the capacitors is included in the circuit.
摘要翻译： 时钟电路与控制电流发生器和与其耦合的比率电路。 本发明的比率电路利用至少两个电容器，每个电容器与相应的晶体管串联耦合并且彼此并联布置。 每个电容晶体管晶体管对与另一个并联并耦合在控制电流发生器和地之间，使得所选择的电容器晶体管串联中的至少一个晶体管可以选择性地截止，而另一个可以由时钟周期直接控制 。 该电路在时钟周期内产生定时边沿，该时钟周期可以是时钟周期的任何一部分，并且包括时钟，受控电流发生器和耦合到时钟和发生器的比率电路。 优选地，该比率电路包括在发生器和地之间并联耦合的至少两个电容 - 晶体管对，其中时钟被耦合到晶体管之一的控制电极，并连接到另一个晶体管的控制电极， 关闭信号源。 用于放电电容器的元件包括在电路中。
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