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    Synchronous memory device utilizing two external clocks
    111.
    发明授权
    Synchronous memory device utilizing two external clocks 失效
    使用两个外部时钟的同步存储器件

    公开(公告)号：US6032215A

    公开(公告)日：2000-02-29

    申请号：US263224

    申请日：1999-03-05

    Applicant: Michael Farmwald ,  Mark Horowitz

    Inventor： Michael Farmwald ,  Mark Horowitz

    IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

    CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

    Abstract: A synchronous memory device includes clock receiver circuitry to receive first and second external clock signals from an external bus. Clock generation circuitry, coupled to the clock receiver circuitry, generates a first internal clock signal having a clock edge which is synchronized with at least the first external clock signal and generates a second internal clock signal having a clock edge which is synchronized with at least the second external clock signal. The memory device further includes a first subarray section and a second subarray section. The first subarray section includes a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location. The second subarray section includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section. The memory device also includes output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request. Multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first driver and couples the first internal I/O line of the second subarray section to an input of the second driver in response to a clock edge of a first internal clock signal; and couples the second internal I/O line of the first subarray section to an input of the first driver and couples the second internal I/O line of the second subarray section to an input of the second driver in response to the clock edge of the second internal clock signal.

    Abstract translation: 同步存储器件包括从外部总线接收第一和第二外部时钟信号的时钟接收器电路。 耦合到时钟接收器电路的时钟产生电路产生具有与至少第一外部时钟信号同步的时钟沿的第一内部时钟信号，并且产生具有时钟沿的第二内部时钟信号，该时钟沿至少与 第二个外部时钟信号。 存储器装置还包括第一子阵列部分和第二子阵列部分。 第一子阵列部分包括用于从第一存储器单元位置访问数据的第一内部I / O线和用于从第二存储器单元位置访问数据的第二内部I / O线。 第二子阵列部分包括用于从第二子阵列部分中的第三存储器单元位置访问数据的第一内部I / O线和用于从第二子阵列部分中的第四存储器单元位置访问数据的第二内部I / O线。 存储器件还包括输出驱动器电路，包括第一输出驱动器和第二输出驱动器，以响应读取请求将数据输出到外部总线上。 多路复用器电路将第一子阵列部分的第一内部I / O线耦合到第一驱动器的输入端，并响应于第二驱动器的时钟沿将第二子阵列部分的第一内部I / O线耦合到第二驱动器的输入端 第一个内部时钟信号; 并且将第一子阵列部分的第二内部I / O线耦合到第一驱动器的输入端，并且响应于第二子阵列的时钟沿将第二子阵列部分的第二内部I / O线耦合到第二驱动器的输入端 第二个内部时钟信号。

    Memory device with a phase locked loop circuitry
    116.
    发明授权
    Memory device with a phase locked loop circuitry 失效
    具有锁相环电路的存储器件

    公开(公告)号：US5657481A

    公开(公告)日：1997-08-12

    申请号：US749729

    申请日：1996-11-15

    Applicant: Michael Farmwald ,  Mark Horowitz

    Inventor： Michael Farmwald ,  Mark Horowitz

    IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G11C8/04

    CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

    Abstract: A clock signal generation apparatus for a memory device of a data processing system is described for generating an internal clock signal for the memory device that is synchronized with an external clock signal. The data processing system includes a transmission line for transmitting a global clock signal to the memory device. A first receiving circuit is coupled to a first point of the transmission line for receiving the global clock signal at the first point and for generating a first local clock signal. A first delay circuitry delays the first local clock signal to be a first delayed clock signal such that the first delayed local clock signal is synchronized with the global clock signal received at the first point of the transmission line. The first delay circuitry provides a first variable delay to the first delayed local clock signal. A second receiving circuit is coupled to the second point of the transmission line for receiving the global clock signal at the second point and for generating a second local clock signal. A second delay circuitry delays the second local clock signal to be a second delayed clock signal such that the second delayed local clock signal is synchronized with the global clock signal received at the second point of the transmission line. The second delay circuitry provides a second variable delay to the second delayed local clock signal. A third delay circuitry is coupled to receive the first and second local clock signals for generating the internal clock signal for the memory device at a timing that is halfway between the first and second local clock signals.

    Abstract translation: 描述了一种用于数据处理系统的存储器件的时钟信号产生装置，用于产生与外部时钟信号同步的存储器件的内部时钟信号。 数据处理系统包括用于将全局时钟信号发送到存储器件的传输线。 第一接收电路耦合到传输线的第一点，用于在第一点接收全局时钟信号并产生第一本地时钟信号。 第一延迟电路将第一本地时钟信号延迟为第一延迟时钟信号，使得第一延迟本地时钟信号与在传输线的第一点接收的全局时钟信号同步。 第一延迟电路为第一延迟本地时钟信号提供第一可变延迟。 第二接收电路耦合到传输线的第二点，用于在第二点接收全局时钟信号，并产生第二本地时钟信号。 第二延迟电路将第二本地时钟信号延迟为第二延迟时钟信号，使得第二延迟本地时钟信号与在传输线的第二点接收的全局时钟信号同步。 第二延迟电路为第二延迟本地时钟信号提供第二可变延迟。 第三延迟电路被耦合以接收第一和第二本地时钟信号，用于在第一和第二本地时钟信号之间的中间位置产生存储器件的内部时钟信号。

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