公开(公告)号：US11295811B2

公开(公告)日：2022-04-05

申请号：US17004259

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Robert J. Gleixner ,  Karthik Sarpatwari

IPC: G11C11/00 ,  G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

公开(公告)号：US20220068377A1

公开(公告)日：2022-03-03

申请号：US17004259

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Robert J. Gleixner ,  Karthik Sarpatwari

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

公开(公告)号：US11222690B2

公开(公告)日：2022-01-11

申请号：US16725261

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C7/00 ,  G11C11/4097 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

公开(公告)号：US11043260B2

公开(公告)日：2021-06-22

申请号：US16722665

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/40 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

公开(公告)号：US20210050045A1

公开(公告)日：2021-02-18

申请号：US16542975

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer

IPC: G11C11/16 ,  G11C11/56 ,  G06F7/58 ,  G06F13/16 ,  G06N3/063

Abstract: An output, representing synaptic weights of a neural network can be received from first memory elements. The output can be compared to a known correct output. A random number can be generated with a tuned bias via second memory elements. The weights can be updated based on the random number and a difference between the output and the known correct output.

公开(公告)号：US20200295005A1

公开(公告)日：2020-09-17

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12219750B2

公开(公告)日：2025-02-04

申请号：US18244069

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: G11C11/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  H01L29/24 ,  H10B12/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20250014641A1

公开(公告)日：2025-01-09

申请号：US18890624

申请日：2024-09-19

Applicant: Micron Technology, Inc.

Inventor： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

IPC: G11C13/00

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

公开(公告)号：US20240413154A1

公开(公告)日：2024-12-12

申请号：US18807741

申请日：2024-08-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240233797A1

公开(公告)日：2024-07-11

申请号：US18615490

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/402 ,  G11C11/409 ,  H01L29/22 ,  H01L29/78 ,  H10B99/00

CPC classification number: G11C11/4023 ,  G11C11/409 ,  H01L29/22 ,  H01L29/7827 ,  H10B99/00

Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.