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235 条记录 (耗时 0.039 秒)

    Micro-oscillating member, light-deflector, and image-forming apparatus
    114.
    发明申请
    Micro-oscillating member, light-deflector, and image-forming apparatus 失效
    微振荡构件，光偏转器和图像形成装置

    公开(公告)号：US20060152785A1

    公开(公告)日：2006-07-13

    申请号：US10544173

    申请日：2004-12-10

    申请人： Susumu Yasuda ,  Yasuhiro Shimada

    发明人： Susumu Yasuda ,  Yasuhiro Shimada

    IPC分类号： G02B26/08

    CPC分类号： G02B26/105 ,  G02B26/085 ,  Y10S359/904

    摘要： The present invention provides a resonance type micro-oscillating member capable of restraining a fluctuation of angular velocity, and specifically provides a micro-oscillating member, which is nested micro-oscillating member, wherein there exist a reference oscillation mode which is the characteristic oscillation mode of a reference frequency, and an even numbered oscillation mode which is the characteristic oscillation mode of a frequency being approximate even number times the reference frequency.

    摘要翻译： 本发明提供一种能够抑制角速度波动的共振型微振荡部件，具体地提供嵌套微振荡部件的微振荡部件，其中存在作为特征振荡模式的基准振荡模式 以及偶数振荡模式，其是频率近似偶数倍的参考频率的特征振荡模式。

    Semiconductor device
    115.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060095975A1

    公开(公告)日：2006-05-04

    申请号：US11212585

    申请日：2005-08-29

    申请人： Takayoshi Yamada ,  Shinzo Koyama ,  Yoshihisa Kato ,  Yasuhiro Shimada

    发明人： Takayoshi Yamada ,  Shinzo Koyama ,  Yoshihisa Kato ,  Yasuhiro Shimada

    IPC分类号： H04L9/32

    CPC分类号： G06F21/79 ,  H04L9/085

    摘要： A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.

    摘要翻译： 本发明的半导体器件包括：用于存储数据的非易失性存储单元中的至少一个; 算术逻辑单元中的至少一个，其可操作以使用存储在存储单元中的数据和从外部输入的数据执行算术运算; 以及输出单元，其可操作以输出由所述算术单元执行的算术逻辑运算的结果; 其中所述存储器单元，所述算术逻辑单元和所述输出单元包括在功能块中，并且所述存储器单元中的每一个的输出线仅与所述算术单元中的至少一个连接。

    Ferroelectric memory and method of operating same
    117.
    发明授权
    Ferroelectric memory and method of operating same 有权
    铁电存储器和操作方法相同

    公开(公告)号：US06924997B2

    公开(公告)日：2005-08-02

    申请号：US10381235

    申请日：2001-09-25

    申请人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

    发明人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

    摘要翻译： 铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息 放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等） 驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。 通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。 在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。