公开(公告)号：US20060033049A1

公开(公告)日：2006-02-16

申请号：US11200176

申请日：2005-08-10

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

IPC分类号： G21K5/10

CPC分类号： H01J37/3026 ,  G03F1/36 ,  G03F1/68

摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

公开(公告)号：US20050177811A1

公开(公告)日：2005-08-11

申请号：US11105431

申请日：2005-04-14

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

IPC分类号： H01L21/66 ,  G06F17/50 ,  B05C11/00 ,  G01R31/26 ,  G03C5/00 ,  G03C8/00 ,  G03F9/00 ,  G06F9/45

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

公开(公告)号：US20130062771A1

公开(公告)日：2013-03-14

申请号：US13405922

申请日：2012-02-27

申请人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

发明人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

IPC分类号： H01L23/48 ,  H01L21/311 ,  G06F17/50

CPC分类号： H01L21/31144 ,  G06F17/5077 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

公开(公告)号：US20120311511A1

公开(公告)日：2012-12-06

申请号：US13399042

申请日：2012-02-17

申请人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Chikaaki Kodama ,  Fumiharu Nakajima

发明人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Chikaaki Kodama ,  Fumiharu Nakajima

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/70 ,  G06F17/5009

摘要： A mask inspection method according to the embodiments, original data corresponding to a semiconductor integrated circuit pattern to be formed on a substrate is created. After that, original production simulation which mocks an original production process is performed on the original data to derive information relating to an original pattern shape in the case of forming an original pattern corresponding to the original data on an original. After that, whether or not the information relating to an original pattern shape satisfies a predetermined value decided based on the original production process is determined.

摘要翻译： 根据实施例的掩模检查方法，产生对应于要形成在基板上的半导体集成电路图案的原始数据。 之后，对原始数据执行原始制作过程的原始制作模拟，以在形成与原始数据相对应的原始图案的情况下导出与原始图案形状有关的信息。 之后，确定与原始图案形状相关的信息是否满足基于原始制作处理决定的预定值。

公开(公告)号：US20120183906A1

公开(公告)日：2012-07-19

申请号：US13237651

申请日：2011-09-20

申请人： Chikaaki KODAMA ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

发明人： Chikaaki KODAMA ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G03F1/36 ,  G03F1/38

摘要： According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern.

摘要翻译： 根据实施例的掩模图案生成方法，当通过使用其中放置辅助图案的掩模图案在衬底上形成衬底上图案时，由于辅助图案而转移到衬底上的不需要的图案， 被提取为不期望的转移模式。 然后，通过根据不希望的转印图案的尺寸和位置改变辅助图案的尺寸来校正掩模图案。

公开(公告)号：US20120127454A1

公开(公告)日：2012-05-24

申请号：US13239449

申请日：2011-09-22

申请人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

发明人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

IPC分类号： G03B27/32

CPC分类号： G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00

摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

摘要翻译： 根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。 存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。 存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案， 区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。 用左图案蚀刻该胶片作为掩模。

公开(公告)号：US08171433B2

公开(公告)日：2012-05-01

申请号：US12554495

申请日：2009-09-04

申请人： Masanori Takahashi ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Masanori Takahashi ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.

摘要翻译： 计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系 由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

公开(公告)号：US07966584B2

公开(公告)日：2011-06-21

申请号：US12385454

申请日：2009-04-08

申请人： Suigen Kyoh ,  Toshiya Kotani ,  Soichi Inoue

发明人： Suigen Kyoh ,  Toshiya Kotani ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

摘要翻译： 公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为 形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

公开(公告)号：US07941767B2

公开(公告)日：2011-05-10

申请号：US12112688

申请日：2008-04-30

申请人： Hidefumi Mukai ,  Shinji Yamaguchi ,  Yukiyasu Arisawa ,  Toshiya Kotani

发明人： Hidefumi Mukai ,  Shinji Yamaguchi ,  Yukiyasu Arisawa ,  Toshiya Kotani

IPC分类号： G06F17/50 ,  G06F19/00 ,  G01B7/00 ,  G06K9/00

CPC分类号： G03F1/82 ,  G03F1/86

摘要： A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.

摘要翻译： 洗涤光掩模，并且测量光掩模的透光率和相位差的至少一个物理量，图案的尺寸，图案的高度和图案的侧壁形状。 之后，测量先前为光掩模确定的边界图案的二维形状。 通过使用测量的物理量对所测量的二维形状进行光刻模拟，导出光刻容限。 然后，是否可以使用光掩模是基于导出的平版印刷公差来确定的。

公开(公告)号：US07934175B2

公开(公告)日：2011-04-26

申请号：US12062859

申请日：2008-04-04

申请人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.

摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。