公开(公告)号：US20110235302A1

公开(公告)日：2011-09-29

申请号：US13064036

申请日：2011-03-02

申请人： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

IPC分类号： H05K7/02

CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and manufacturing method to effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.

摘要翻译： 一种半导体器件和制造方法，用于有效地抑制电感器元件和位于同一芯片上形成的电感器元件上方的电线之间发生相互作用的问题。 半导体器件包括半导体衬底和覆盖该半导体衬底的多层布线层，多层布线层包括：电感器元件和三个连续的布线和形成在电感器元件上方的第四布线; 和两个固定电压电位的屏蔽导体，从平面图可以看到电感器元件，并形成在电感器元件和三个连续的导线之间，并形成在电感器元件上方的第四根导线。

公开(公告)号：US07999392B2

公开(公告)日：2011-08-16

申请号：US11908099

申请日：2006-03-09

申请人： Hiroto Ohtake ,  Yoshihiro Hayashi

发明人： Hiroto Ohtake ,  Yoshihiro Hayashi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/11

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.

摘要翻译： 根据本发明的多层互连结构应用于以细间距形成多个互连并且通孔连接到至少一个互连的情况。 在多层互连结构中，面向通孔的区域至少在与连接到通孔的互连件相邻的互连件的互连（面对通孔）的局部变窄。

公开(公告)号：US07968471B2

公开(公告)日：2011-06-28

申请号：US10580606

申请日：2004-11-29

申请人： Yoshimichi Harada ,  Yoshihiro Hayashi ,  Fuminori Itoh ,  Kenichiro Hijioka ,  Tsuneo Takeuchi

发明人： Yoshimichi Harada ,  Yoshihiro Hayashi ,  Fuminori Itoh ,  Kenichiro Hijioka ,  Tsuneo Takeuchi

IPC分类号： H01L21/31

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating film. Gas containing molecule vapor of at least one or more organic silica compounds, which have a cyclic silica skeleton in its molecule and have at least one or more unsaturated hydrocarbon groups bound with the cyclic silica skeleton is introduced into plasma to grow a porous insulating film on a semiconductor substrate.

摘要翻译： 本发明提供一种制造作为构成半导体器件的绝缘膜有效的多孔绝缘膜的方法以及与半导体材料具有高粘合性的多孔绝缘膜的制造方法，所述半导体材料与所述半导体材料的上下界面接触 绝缘膜。 在其分子中具有环状二氧化硅骨架并且具有与环状二氧化硅骨架结合的至少一个以上不饱和烃基的至少一种以上有机二氧化硅化合物的含有气体的分子蒸气被引入等离子体中以在多孔绝缘膜上生长多孔绝缘膜 半导体衬底。

公开(公告)号：USD640230S1

公开(公告)日：2011-06-21

申请号：US29382111

申请日：2010-12-29

申请人： Koji Sakai ,  Yoshihiro Hayashi

设计人： Koji Sakai ,  Yoshihiro Hayashi

公开(公告)号：USD640229S1

公开(公告)日：2011-06-21

申请号：US29382110

申请日：2010-12-29

申请人： Koji Sakai ,  Yoshihiro Hayashi

设计人： Koji Sakai ,  Yoshihiro Hayashi

公开(公告)号：USD626162S1

公开(公告)日：2010-10-26

申请号：US29344776

申请日：2009-10-05

申请人： Koji Suzuki ,  Yoshihiro Hayashi ,  Kenji Tajima ,  Masayoshi Karasawa ,  Keiji Shimizu

设计人： Koji Suzuki ,  Yoshihiro Hayashi ,  Kenji Tajima ,  Masayoshi Karasawa ,  Keiji Shimizu

公开(公告)号：US20100219512A1

公开(公告)日：2010-09-02

申请号：US11991745

申请日：2006-09-08

申请人： Munehiro Tada ,  Naoya Furutake ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

发明人： Munehiro Tada ,  Naoya Furutake ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

IPC分类号： H01L23/29 ,  H01L21/47

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming porous insulating film using cyclic siloxane raw material monomer is provided, which method suppresses detachment of hydrocarbon and is able to form a low-density film.In a method where at least cyclic organosiloxane raw material 101 is supplied to a reaction chamber and an insulating film is formed by plasma vapor deposition method, above-mentioned problem is solved by a method for a forming porous insulating film using the mixed gas of a cyclic organosiloxane raw material 101 and a compound raw material 103 including a part of chemical structure comprising the cyclic organosiloxane raw material 101. The compound raw material 103 is preferably a compound including a part of side chain of the cyclic organosiloxane raw material 101.

摘要翻译： 提供了使用环状硅氧烷原料单体形成多孔绝缘膜的方法，该方法抑制烃的分离并能够形成低密度膜。 在通过等离子体气相沉积法将至少环状有机硅氧烷原料101供给到反应室并形成绝缘膜的方法中，上述问题通过使用以下的混合气体形成多孔绝缘膜的方法来解决： 环状有机硅氧烷原料101和包含环状有机硅氧烷原料101的化学结构的一部分的复合原料103.化合物原料103优选为包含环状有机硅氧烷原料101的侧链的一部分的化合物。

公开(公告)号：US07750413B2

公开(公告)日：2010-07-06

申请号：US10561089

申请日：2004-06-16

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

IPC分类号： H01L29/76

CPC分类号： H01L28/10 ,  H01L21/8221 ,  H01L23/5227 ,  H01L23/552 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/08 ,  H01L29/0657 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/80001

摘要： An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip.MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.

摘要翻译： 本发明的目的是将包括其中形成的电感器的RF电路和数字电路安装在单个芯片上。 在由元件隔离膜2隔离的区域中的半导体衬底1上形成MOSFET。多个低介电常数绝缘棒包括嵌入其中的低介电常数绝缘体，并穿透第一层间电介质膜4以到达硅衬底的内部 设置在RF电路区域100中。电感器40通过使用多层互连在RF电路区域中的层间电介质膜上形成。 在电感器的芯部及其周围的区域中形成有高导磁率隔离区域，其中包括高导磁率材料和低电容率材料的混合物的复合材料。

公开(公告)号：US20100006976A1

公开(公告)日：2010-01-14

申请号：US12530729

申请日：2008-02-27

申请人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/76 ,  H01L21/20

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L27/016 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides a semiconductor device having a capacitor with reduced deterioration of dielectric constant and reduced leakage between upper and lower electrodes and a manufacturing method of such a semiconductor device. A capacity structure is configured by sequentially stacking a lower electrode, a capacitive insulation film, and an upper electrode on wiring or a contact plug. The capacity structure is of a thin-film capacitor structure having, at the interface between the lower electrode and the capacitive insulation film, a thin metal film having insulating properties and exhibiting a high dielectric constant.

摘要翻译： 本发明提供一种具有电容器的半导体器件，其具有降低的介电常数降低和上下电极之间的泄漏减少以及这种半导体器件的制造方法。 容量结构通过在布线或接触插塞上依次堆叠下电极，电容绝缘膜和上电极而构成。 该容量结构是薄膜电容器结构，在下电极和电容绝缘膜之间的界面处具有绝缘性能并呈现高介电常数的薄金属膜。

公开(公告)号：US20090315662A1

公开(公告)日：2009-12-24

申请号：US12375944

申请日：2007-08-01

申请人： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

IPC分类号： H01F5/00 ,  H01F41/04

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/004 ,  H01F2017/0086 ,  Y10T29/4902 ,  Y10T29/49071

摘要： An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

摘要翻译： 电感器元件形成在多层引线结构中，该多层引线结构包括引线，绝缘层和绝缘层，绝缘层和设置在绝缘层中的通孔以及连接引线上和下的引线层是多层叠层，其特征在于： 至少一对垂直相邻引线的至少一部分是线圈引线; 线圈引线串联连接，其中垂直相邻的线圈引线的电流方向通过设置在其端部上的通孔相同，并形成串联电感; 并且垂直相邻的线圈引线的引线间电容大于形成在同一引线层中的其它线圈引线之间的引线间电容。