公开(公告)号：US11410951B2

公开(公告)日：2022-08-09

申请号：US17207242

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C11/408 ,  H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

公开(公告)号：US11322499B2

公开(公告)日：2022-05-03

申请号：US16943019

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US11133315B2

公开(公告)日：2021-09-28

申请号：US16564071

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L29/49

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device comprises a substrate having a trench, a gate dielectric layer covering a surface of the trench, a gate electrode filling a lower portion of the trench, a capping pattern on the gate electrode in the trench, and a work function control pattern between the gate electrode and the capping pattern in the trench. The gate dielectric layer comprises a first segment having a first thickness between the gate electrode and the trench and a second segment having a second thickness between the capping pattern and the trench. The second thickness is less than the first thickness.

公开(公告)号：US11088143B2

公开(公告)日：2021-08-10

申请号：US16896470

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11037930B2

公开(公告)日：2021-06-15

申请号：US16670232

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Huijung Kim ,  Sohyun Park ,  Jaehwan Cho ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.

公开(公告)号：US10720211B2

公开(公告)日：2020-07-21

申请号：US16458594

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  G11C13/00 ,  G11C5/02 ,  G11C11/00 ,  H01L45/00 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US10483346B2

公开(公告)日：2019-11-19

申请号：US16115690

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyung Nam ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L29/41 ,  H01L49/02 ,  H01L27/108 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/112

Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

公开(公告)号：US10468350B2

公开(公告)日：2019-11-05

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US10410916B2

公开(公告)日：2019-09-10

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Jiseok Hong ,  Kiseok Lee ,  Jemin Park ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

公开(公告)号：US20190088739A1

公开(公告)日：2019-03-21

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.