公开(公告)号：US11075179B2

公开(公告)日：2021-07-27

申请号：US16430075

申请日：2019-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Yi-Ming Dai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.

公开(公告)号：US20210210534A1

公开(公告)日：2021-07-08

申请号：US16736134

申请日：2020-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Chia Ching Liao ,  Yen-Yu Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

公开(公告)号：US20210175076A1

公开(公告)日：2021-06-10

申请号：US17181970

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

公开(公告)号：US10916517B2

公开(公告)日：2021-02-09

申请号：US16727628

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L23/525 ,  H01L21/02 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20200273966A1

公开(公告)日：2020-08-27

申请号：US16870360

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L21/285 ,  H01L21/768

Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.

公开(公告)号：US10748806B2

公开(公告)日：2020-08-18

申请号：US16230765

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Wei-Jen Chen ,  Yi-Chen Chiang ,  Tsang-Yang Liu ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

IPC: H01L21/687

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

公开(公告)号：US10651066B2

公开(公告)日：2020-05-12

申请号：US15879651

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Powen Huang ,  Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00 ,  B08B3/04

Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier using a transportation apparatus. The method further includes measuring an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool positioned on the wafer carrier during the movement of the wafer carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.

公开(公告)号：US10354965B2

公开(公告)日：2019-07-16

申请号：US15719370

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Chun-Chih Lin ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Wen-Hao Cheng

IPC: H01L23/52 ,  H01L23/00

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

公开(公告)号：US10345716B2

公开(公告)日：2019-07-09

申请号：US15877646

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: G03F7/20

Abstract: A method for fault detection in a fabrication system is provided. The method includes transferring a reticle carrier containing a reticle from an original position to a destination position. The method further includes detecting environmental condition in the reticle carrier during the transfer of the reticle carrier using a metrology tool that is positioned at the reticle carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.

公开(公告)号：US20190139828A1

公开(公告)日：2019-05-09

申请号：US16199498

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.