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310 条记录 (耗时 0.044 秒)

    SDRAM with command decoder coupled to address registers
    112.
    发明授权
    SDRAM with command decoder coupled to address registers 失效
    SDRAM与命令解码器耦合到地址寄存器

    公开(公告)号：US06910096B2

    公开(公告)日：2005-06-21

    申请号：US10452339

    申请日：2003-06-02

    申请人： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    发明人： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    IPC分类号： G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00 ,  G06F12/02

    CPC分类号： G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

    摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

    摘要翻译： 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

    Turn-signal automatic cancellation apparatus
    114.
    发明授权
    Turn-signal automatic cancellation apparatus 失效
    转向信号自动取消装置

    公开(公告)号：US06483430B2

    公开(公告)日：2002-11-19

    申请号：US09899181

    申请日：2001-07-06

    申请人： Takeo Okuda ,  Masashi Hashimoto ,  Yoshinori Ito ,  Minoru Morikawa

    发明人： Takeo Okuda ,  Masashi Hashimoto ,  Yoshinori Ito ,  Minoru Morikawa

    IPC分类号： B60Q140

    CPC分类号： B60Q1/40

    摘要： A control circuit generates a right-turn or left-turn signal from a direction indicator lamp based on a direction indicating signal from a turn signal switch in a scooter as a vehicle. The control circuit then calculates a turning angle of the scooter from an angular speed V of the scooter detected by an angular speed sensor, and cancels the turn signal generated from the direction indicator lamp on the condition that the turning angle be equal to or greater than a reference turning angle, that a vehicle speed N detected by a vehicle speed sensor be equal to or higher than a reference vehicle speed, and that the angular speed detected by the angular speed sensor be equal to or lower than a reference angular speed. Accordingly, even when the scooter is waiting to make a right or left turn at an intersection with a turning angle equal to or greater than the reference turning angle and an angular speed V equal to or lower than the reference angular speed, the vehicle speed N does not become equal to or higher than the reference vehicle speed (the vehicle speed is actually zero). Therefore, the turn signal is prevented from being canceled unnecessarily.

    摘要翻译： 控制电路基于来自作为车辆的踏板车中的转向信号开关的方向指示信号，从方向指示灯产生右转或左转信号。 然后，控制电路从角速度传感器检测出的踏板车的角速度V计算踏板车的转弯角度，并且在转向角度等于或大于 由车速传感器检测到的车速N等于或高于基准车速，并且由角速度传感器检测的角速度等于或低于参考角速度的参考转向角。 因此，即使当踏板车等待在等于或大于基准转弯角度的转弯角度和等于或小于参考角速度的角速度V的交点处进行右转或左转时，车速N 不等于或高于参考车速（车速实际上为零）。 因此，防止转向信号不必要地被取消。

    Access time measurement circuit and method
    116.
    发明授权
    Access time measurement circuit and method 失效
    访问时间测量电路和方法

    公开(公告)号：US06266749B1

    公开(公告)日：2001-07-24

    申请号：US09041264

    申请日：1998-03-12

    申请人： Masashi Hashimoto ,  James N. Hall

    发明人： Masashi Hashimoto ,  James N. Hall

    IPC分类号： G06F1100

    CPC分类号： G11C29/56 ,  G01R31/31937 ,  G11C29/50

    摘要： A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”. For a clock signal having a pulse length or duty cycle that is longer than the access time of the memory circuit, the output of the storage element matches the data pattern stored by the test circuitry. As the clock frequency is increased, or the duty cycle decreased, so that the pulse length approximates the access time, the data output from the storage element no longer matches the data expected by the test circuitry, thus allowing a determination of the access time.

    摘要翻译： 一种用于测量存储电路的存取时间的电路。 电路包括具有输入端子，输出端子和时钟端子的存储元件908。 存储元件的输入端耦合到存储器电路900的输出。时钟信号源906耦合到存储元件的时钟端子和存储器电路的时钟端子。 电路还包括耦合到存储器电路的地址和控制端子以及存储元件的输出端子的测试电路902。 测试电路可操作以存储或生成测试数据模式，并将模式与存储元件输出的数据进行比较。 在一个实施例中，存储元件是包括与触发器串联耦合的使能时钟的反相器的数据锁存器。 在一个实施例中，触发器是交叉耦合的逆变器存储单元或“保持器”。 对于具有比存储器电路的访问时间长的脉冲长度或占空比的时钟信号，存储元件的输出与由测试电路存储的数据模式相匹配。 随着时钟频率增加或占空比减小，使得脉冲长度接近访问时间，从存储元件输出的数据不再与测试电路预期的数据匹配，从而允许确定访问时间。

    Process of synchronously writing data to a dynamic random access memory array
    117.
    发明授权
    Process of synchronously writing data to a dynamic random access memory array 失效
    将数据同步写入动态随机存取存储器阵列的过程

    公开(公告)号：US06188635B1

    公开(公告)日：2001-02-13

    申请号：US08488231

    申请日：1995-06-07

    申请人： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    发明人： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    IPC分类号： G11C800

    CPC分类号： G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

    摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

    摘要翻译： 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

    Semiconductor memory device for storing data with efficient page access of data lying in a diagonal line of a two-dimensional data construction
    118.
    发明授权
    Semiconductor memory device for storing data with efficient page access of data lying in a diagonal line of a two-dimensional data construction 有权
    用于存储数据的半导体存储器件，其具有位于二维数据结构的对角线中的数据的有效页访问

    公开(公告)号：US6115323A

    公开(公告)日：2000-09-05

    申请号：US185685

    申请日：1998-11-04

    申请人： Masashi Hashimoto

    发明人： Masashi Hashimoto

    IPC分类号： G11C11/401 ,  G06F12/06 ,  G11C8/12 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C8/12

    摘要： The objective of the invention is to conduct access of image data in the diagonal direction at high-speed by using the page mode.The memory region is divided into four memory arrays (15.sub.-1 to 15.sub.-4), and shifters (13.sub.-1 to 13.sub.-4) [sic: (14.sub.-1 to 14.sub.-4)] are provided that can shift the page address by one address in relation to each memory array. The image data are divided into sub-blocks of 4.times.4, 4 data items for the vertical correction are stored in the same memory array, and the page addresses for the sub-blocks connected in the horizontal direction are stored so as to be consecutive. In the case of accessing the data in the diagonal direction, when the data straddle adjacent blocks 4 at a time from the top, the page address is shifted by a shifter for the memory array containing that straddled column. In this way even in accessing the diagonal direction, 4 units of data are always obtained for a 1-page access, and data scanning of the diagonal direction by the page mode becomes possible.

    摘要翻译： 本发明的目的是通过使用页面模式来高速地在对角线方向上访问图像数据。 存储区域被分成四个存储器阵列（15-1至15-4），并且提供可以移动页面的移位器（13-1至13-4）[sic：（14-1至14-4）] 根据每个存储器阵列的一个地址来寻址。 图像数据被划分为4×4的子块，用于垂直校正的4个数据项存储在相同的存储器阵列中，并且存储在水平方向上连接的子块的页地址以便连续。 在对角方向访问数据的情况下，当数据从顶部一次跨越相邻块4时，页面地址被包含该跨置列的存储器阵列的移位器移位。 以这种方式，即使在访问对角线方向时，总是获得4个单位的数据用于1页访问，并且通过页面模式的对角线方向的数据扫描成为可能。

    Apparatus and method for transistor element reduction in circuits comparing serial data signals
    119.
    发明授权
    Apparatus and method for transistor element reduction in circuits comparing serial data signals 失效
    比较串行数据信号的电路中晶体管元件降低的装置和方法

    公开(公告)号：US6043686A

    公开(公告)日：2000-03-28

    申请号：US861509

    申请日：1997-05-22

    申请人： Masashi Hashimoto ,  Anjana Ghosh

    发明人： Masashi Hashimoto ,  Anjana Ghosh

    IPC分类号： G06F7/02 ,  H03K19/096 ,  H03K19/21

    CPC分类号： H03K19/215 ,  G06F7/02 ,  H03K19/0963

    摘要： In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

    摘要翻译： 在用于比较串行数据信号的集成电路的设计中，可以通过基于相关联的真值表实现比较门（12）而不是通过使用通用比较门分量来减少晶体管元件的数量。 使用这种方法，可以使用两个晶体管元件（221,222）来实现异或门（22），可以使用两个晶体管元件（521,522），与门（62）222来实现异或门（52） 可以使用单个晶体管元件（621）来实现，并且可以使用单个晶体管元件（721）来实现或门（72）。 用于实现比较门的元件数量减少可以提供一个节省相关电路的晶体管元件。

    Pipeline image processing method and device for computing image block on half-grid
    120.
    发明授权
    Pipeline image processing method and device for computing image block on half-grid 失效
    用于计算半网格图像块的管道图像处理方法和装置

    公开(公告)号：US5878173A

    公开(公告)日：1999-03-02

    申请号：US730993

    申请日：1996-10-16

    申请人： Masashi Hashimoto ,  Hirohisa Yamaguchi

    发明人： Masashi Hashimoto ,  Hirohisa Yamaguchi

    IPC分类号： G09G3/20 ,  G06T1/60 ,  G06T9/00 ,  G09G5/00 ,  G09G5/36 ,  G11C7/00 ,  G11C11/401 ,  H04N5/14 ,  H04N5/907 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/50 ,  H04N19/59 ,  G06T1/20

    CPC分类号： G11C7/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61 ,  H04N5/14 ,  H04N5/907

    摘要： Method and device for enabling high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operation of MPEG, etc. Eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-pel operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.

    摘要翻译： 用于以块为单位实现图像信息的高速写入/读取操作的方法和装置，以便完全满足对MPEG等的高速操作的需求。八个存储器阵列MA1-MA8并行连接在图像存储器 单位10 因此，在每个存储器阵列MAi中，可以在写入地址生成电路12，存储器阵列控制逻辑14和读取地址生成电路16的控制下单独地写入/读取图像。存储器阵列MA1-MA8的输入/输出端子被连接 通过输入/输出缓冲器18的八个数据寄存器DREG1-DREG8，选择器电路20的八个行选择器YSEL1-YSEL8和列选择器XSEL以及数据总线22耦合到半像素操作电路24。