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公开(公告)号：US12029044B2
公开(公告)日：2024-07-02
申请号：US18127651
申请日：2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
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公开(公告)号：US11968911B2
公开(公告)日：2024-04-23
申请号：US17518571
申请日：2021-11-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.
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公开(公告)号：US11956973B2
公开(公告)日：2024-04-09
申请号：US17369917
申请日：2021-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.
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公开(公告)号：US11950513B2
公开(公告)日：2024-04-02
申请号：US17857185
申请日：2022-07-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10N50/01 , H01F10/3254 , H01F10/329 , H10N50/80
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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公开(公告)号：US11944016B2
公开(公告)日：2024-03-26
申请号：US17692203
申请日：2022-03-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
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Patent Agency Ranking
公开(公告)号：US20240074209A1
公开(公告)日：2024-02-29
申请号：US18500994
申请日：2023-11-02
Applicant: UNITED MICROELECTRONICS CORP
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
CPC classification number: H10B61/00 , G11C11/161 , H01F10/3254 , H01F41/34 , H01L23/5226 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US11895848B2
公开(公告)日：2024-02-06
申请号：US17750386
申请日：2022-05-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10B61/22 , H01L23/528 , H10N50/80 , G11C11/161 , H01F10/3254 , H10N50/85
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
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公开(公告)号：US20230403941A1
公开(公告)日：2023-12-14
申请号：US18238520
申请日：2023-08-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
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公开(公告)号：US20230238043A1
公开(公告)日：2023-07-27
申请号：US18127651
申请日：2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H10B61/00 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
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公开(公告)号：US11646069B2
公开(公告)日：2023-05-09
申请号：US17460348
申请日：2021-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H01L27/222 , H01L27/224 , H01L43/02 , H01L43/12
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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