公开(公告)号：US07106120B1

公开(公告)日：2006-09-12

申请号：US10625647

申请日：2003-07-22

申请人： Sheng Teng Hsu

发明人： Sheng Teng Hsu

IPC分类号： H03L5/00

CPC分类号： G11C16/3436 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2211/5634 ,  G11C2213/31

摘要： Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatably with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit for generating a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

摘要翻译： 使用可编程电阻材料进行匹配电阻，电阻微调电路设计为可逆地修整匹配电阻以匹配参考电阻。 诸如金属非晶硅金属材料，相变材料或钙钛矿材料的可编程电阻材料通常用于电阻存储器件中，并且具有通过施加的电脉冲可逆地和可重复地改变电阻的能力。 本发明的可逆电阻微调电路包括匹配电阻器的电阻桥网络和参考电阻器，以向比较器电路提供输入，以产生指示电阻差的比较信号。 该比较信号可用于控制反馈电路以向匹配电阻器提供适当的电脉冲以修改匹配电阻器的电阻以匹配参考电阻器的电阻。

公开(公告)号：US07098496B2

公开(公告)日：2006-08-29

申请号：US11184659

申请日：2005-07-18

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.

摘要翻译： 本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。 通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了捕获的电荷效应并导致存储保持率的提高 特点 电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。 掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

公开(公告)号：US07098101B1

公开(公告)日：2006-08-29

申请号：US11297242

申请日：2005-12-07

申请人： Tingkai Li ,  Lawrence J. Charneski ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Lawrence J. Charneski ,  Sheng Teng Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L45/1616 ,  C23C16/40 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of forming PrXCa1-xMnO3 thin films having a PMO/CMO super lattice structure using metalorganic chemical vapor deposition includes preparing organometallic compounds and solvents and mixing organometallic compounds and solvents to form PMO and CMO precursors. The precursors for PMO and CMO are injected into a MOCVD chamber vaporizer. Deposition parameters are selected to form a nano-sized PCMO thin film or a crystalline PCMO thin film from the injection of PMO and CMO precursors, wherein the PMO and CMO precursors are alternately injected into the MOCVD chamber vaporizer. The selected deposition parameters are maintained to deposit the PCMO thin film species having a desired Pr:Ca concentration ratio in a specific portion of the PCMO thin film. The resultant PCMO thin film is annealed at a selected temperature for a selected time period.

摘要翻译： 使用金属有机化学气相沉积法形成具有PMO / CMO超晶格结构的Pr 1 x 1 Mn x Mn 3 O 3薄膜的方法包括制备 有机金属化合物和溶剂，并混合有机金属化合物和溶剂以形成PMO和CMO前体。 将PMO和CMO的前体注入到MOCVD室蒸发器中。 选择沉积参数以从注入PMO和CMO前体形成纳米尺寸的PCMO薄膜或结晶PCMO薄膜，其中PMO和CMO前体交替地注入到MOCVD室蒸发器中。 保持所选择的沉积参数以在PCMO薄膜的特定部分沉积具有所需Pr:Ca浓度比的PCMO薄膜种类。 所得PCMO薄膜在所选择的温度下退火选定的时间段。

公开(公告)号：US07098043B2

公开(公告)日：2006-08-29

申请号：US10759468

申请日：2004-01-15

申请人： Wei-Wei Zhuang ,  Lisa H. Stecker ,  Gregory M. Stecker ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Lisa H. Stecker ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1683

摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.

摘要翻译： 提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。 该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

公开(公告)号：US07053403B1

公开(公告)日：2006-05-30

申请号：US11339876

申请日：2006-01-26

申请人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC分类号： H01L29/10 ,  H01L29/12

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US07037856B1

公开(公告)日：2006-05-02

申请号：US11149883

申请日：2005-06-10

申请人： Jer-Shen Maa ,  Douglas J. Tweet ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Douglas J. Tweet ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823807

摘要： A method of fabricating a germanium film on a silicon substrate includes preparing a silicon substrate; depositing a first germanium film to form a continuous germanium film on the silicon substrate; annealing the silicon substrate and the germanium film thereon in a first annealing process to relax the germanium film; depositing a second germanium film on the first germanium film to form a germanium layer; patterning and etching the germanium layer; depositing a layer of dielectric material on the germanium layer; cyclic annealing the silicon substrate having the germanium layer and dielectric material thereon; and completing a device containing the silicon substrate and germanium layer.

摘要翻译： 在硅衬底上制造锗膜的方法包括制备硅衬底; 沉积第一锗膜以在硅衬底上形成连续的锗膜; 在第一退火工艺中将硅衬底和锗膜退火以使锗膜松弛; 在第一锗膜上沉积第二锗膜以形成锗层; 图案化和蚀刻锗层; 在锗层上沉积介电材料层; 对其上具有锗层和介电材料的硅衬底进行循环退火; 并完成包含硅衬底和锗层的器件。

公开(公告)号：US07022621B1

公开(公告)日：2006-04-04

申请号：US11013804

申请日：2004-12-15

申请人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US07015147B2

公开(公告)日：2006-03-21

申请号：US10625065

申请日：2003-07-22

申请人： Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/302

CPC分类号： H01L29/66772 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78639 ,  H01L29/78654

摘要： A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1−xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGex layer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGex layer to remove substantially all of the Si1−xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

摘要翻译： 使用Si 1-x Ge层的选择性蚀刻制造无硅无硅（SON）MOSFET的方法包括制备硅衬底; 在硅衬底上生长外延Si 1-x Ge层x层; 在外延Si 1-x Ge层上生长外延薄顶硅层; 将硅和Si 1-x N x X x x沟槽蚀刻到硅衬底中以形成第一沟槽; 选择性地蚀刻Si 1-x Ge Ge层，以便基本上除去所有的Si 1-x N x Ge x Si 形成气隙; 通过CVD沉积SiO 2层以填充第一沟槽; 从第二沟槽进行沟槽蚀刻; 选择性地蚀刻剩余的Si 1-x N Ge x层; 通过CVD沉积SiO 2的第二层以填充第二沟槽，从而使源极，漏极和沟道与衬底去耦合; 并通过最先进的CMOS制造技术完成结构。

公开(公告)号：US06897530B2

公开(公告)日：2005-05-24

申请号：US10261447

申请日：2002-09-30

申请人： Sheng Teng Hsu

发明人： Sheng Teng Hsu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm. A method of forming an ultra-thin SOI MOS transistor includes preparing a silicon wafer, including forming a top silicon layer having a thickness of between about 100 nm to 200 nm, thinning the top silicon layer to a thickness of between about 10 nm to 30 nm, and forming an oxide layer over the top silicon layer; forming a layer of material taken from the group of material consisting of polysilicon and silicide; forming an oxide cap on the formed layer of material, and etching the oxide cap and layer of material to form a main gate electrode and an auxiliary gate electrode on either side thereof; forming an oxide layer over the structure and etching the oxide layer to form sidewall oxide structures about the gate electrodes; depositing a layer of material taken from the group of material consisting of polysilicon, silicide and metal, etching the newly deposited layer of material, and metallizing the structure.

摘要翻译： 晶体管结构包括厚度小于或等于30nm的主栅极硅有源区; 以及位于所述主栅极硅有源区两侧的辅助栅极有源区，所述辅助栅极有源区与所述主栅极有源区间隔开约200nm的距离。 形成超薄SOI MOS晶体管的方法包括制备硅晶片，其包括形成厚度在约100nm至200nm之间的顶部硅层，将顶部硅层变薄至约10nm至30nm的厚度 并且在顶部硅层上形成氧化物层; 形成从由多晶硅和硅化物组成的材料组中取出的材料层; 在所形成的材料层上形成氧化物盖，蚀刻氧化物盖和材料层，以在其两侧形成主栅电极和辅助栅电极; 在所述结构上形成氧化物层并蚀刻所述氧化物层以形成围绕所述栅电极的侧壁氧化物结构; 沉积从由多晶硅，硅化物和金属组成的材料组中取出的材料层，蚀刻新沉积的材料层，并对结构进行金属化。

公开(公告)号：US06897074B1

公开(公告)日：2005-05-24

申请号：US10794736

申请日：2004-03-03

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L41/22

CPC分类号： H01L21/31691 ,  H01L28/55 ,  H01L41/317

摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

摘要翻译： 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。