公开(公告)号：US20080165589A1

公开(公告)日：2008-07-10

申请号：US11969856

申请日：2008-01-04

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/22

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 一种用于在包括串行外设接口存储器件的集成电路中读取的双I / O数据的方法。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20080123406A1

公开(公告)日：2008-05-29

申请号：US11555849

申请日：2006-11-02

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.

摘要翻译： 用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。 感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。 第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。 在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

公开(公告)号：US20100007377A1

公开(公告)日：2010-01-14

申请号：US12564789

申请日：2009-09-22

申请人： Chun-Hsiung Hing ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hing ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： H03K19/173

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described.

摘要翻译： 集成电路装置包括适于接收支持第一配置的地址的第一命令的串行外围接口，其中，所述串行外设接口在接收到第二命令时支持第二配置的地址，所述第二配置不同于所述第一配置 组态。 在具体实施例中，第一和第二配置的地址长度不同。 在另一个实施例中，与第二命令协作的第二地址具有第一部分和第二部分，第二部分包括多个字节地址，每个字节地址与对应的数据字节相关联。 在另一实施例中，集成电路装置还包括用于控制第一命令和第二命令的操作的模式逻辑电路。 还描述了各种其它实施例。

公开(公告)号：US5734290A

公开(公告)日：1998-03-31

申请号：US616882

申请日：1996-03-15

申请人： Kuen-Long Chang ,  Jieh-Tsorng Wu

发明人： Kuen-Long Chang ,  Jieh-Tsorng Wu

IPC分类号： H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073

摘要： A charge pumping circuit includes a plurality of cascaded voltage gain circuit stages. Each circuit stage has an switching transistor with a source connected electrically to a drain of the transistor of an immediately succeeding one of the circuit stages, and a gate connected electrically to the source of the transistor of the immediately succeeding one of the circuit stages, and a capacitor. The capacitor of odd ones of the circuit stages is connected electrically across a first clock and the source of the transistor of the respective circuit stage. The capacitor of even ones of the circuit stages is connected electrically across a second clock, which is out of phase with the first clock, and the source of the transistor of the respective circuit stage. An output transistor has a drain connected electrically to the source of the transistor of a last voltage gain circuit stage, a source serving as an output terminal of the charge pumping circuit, and a gate connected electrically to the drain of the output transistor. An output capacitor is connected electrically across the source of the output transistor and the first clock when the total number of the voltage gain circuit stages is an even number and across the source of the output transistor and the second clock when the total number of the voltage gain circuit stages is an odd number.

摘要翻译： 电荷泵浦电路包括多个级联的电压增益电路级。 每个电路级具有开关晶体管，其源极电连接到紧接着的一个电路级的晶体管的漏极，以及电连接到紧接着的一个电路级的晶体管的源极的栅极，以及 一个电容器。 电路级的奇数电容器在第一时钟和相应电路级的晶体管的源极之间电连接。 电路级的偶数电容器与第一个时钟不相位的第二个时钟和相应电路级晶体管的源极电连接。 输出晶体管具有与最后的电压增益电路级的晶体管的源极电连接的漏极，用作电荷泵浦电路的输出端的源极和与输出晶体管的漏极电连接的栅极。 当输出晶体管的总数和电压增益电路级的总数为偶数并且跨越输出晶体管的源极和第二时钟时，输出电容器电连接在输出晶体管的源极和第一时钟上， 增益电路级是奇数。

公开(公告)号：US20120092940A1

公开(公告)日：2012-04-19

申请号：US12907263

申请日：2010-10-19

申请人： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

发明人： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC分类号： G11C7/12 ,  G11C7/06

CPC分类号： G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.

摘要翻译： 存储器件的读操作。 响应于指示从不同页面读取数据的输入地址，所选择的字线，第一和第二全局位线和所选择的第一位线组被预充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线被保持预充电。 产生流过所选字线的第二单元电流。 产生第二个参考电流。 基于第二单元电流和第二参考电流来读取第二半页数据。

公开(公告)号：US5745410A

公开(公告)日：1998-04-28

申请号：US619485

申请日：1996-03-21

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

IPC分类号： G11C11/40

CPC分类号： G11C11/40

摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。 第WO97 / 19452号公报 日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。 本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。 在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。 在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。 在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

公开(公告)号：US09092649B2

公开(公告)日：2015-07-28

申请号：US12395776

申请日：2009-03-02

申请人： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

发明人： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

IPC分类号： G06F13/00 ,  G06F21/79 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/42

CPC分类号： G06F21/79 ,  G06F3/062 ,  G06F3/0646 ,  G06F3/0668 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0623 ,  G06F13/4234

摘要： A data protecting method for a memory, which comprising a volatile memory and a non-volatile memory for storing data and data protection information, comprises the following steps. Firstly, load the data protection information to the volatile memory from the non-volatile memory. Next, protect the data stored in the memory according to the data protection information stored in the volatile memory.

摘要翻译： 一种用于存储器的数据保护方法，包括易失性存储器和用于存储数据和数据保护信息的非易失性存储器，包括以下步骤。 首先，将数据保护信息从非易失性存储器加载到易失性存储器。 接下来，根据存储在易失性存储器中的数据保护信息保护存储在存储器中的数据。

公开(公告)号：US20120075943A1

公开(公告)日：2012-03-29

申请号：US12893235

申请日：2010-09-29

申请人： Chia-Jung Chen ,  Su-Chueh Lo ,  Chin-Hung Chang ,  Chen-Chia Fan ,  Kuen-Long Chang

发明人： Chia-Jung Chen ,  Su-Chueh Lo ,  Chin-Hung Chang ,  Chen-Chia Fan ,  Kuen-Long Chang

IPC分类号： G11C29/04

CPC分类号： G11C29/808

摘要： A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses.

摘要翻译： 第一冗余列用于修复存储器单元阵列中的多个缺陷。 缺陷包括阵列中的多个主列的不同主列中的至少第一缺陷和第二缺陷。 然而，由第一冗余列修复的所有多个缺陷不需要在不同的主列中。 该阵列被布置成由行地址和由列地址访问的多个主列访问的多行。

公开(公告)号：US20110173512A1

公开(公告)日：2011-07-14

申请号：US13070008

申请日：2011-03-23

申请人： Wen-Chiao HO ,  Ching-Hung Chang ,  Chung-Hsiung Hung ,  Kuen-Long Chang

发明人： Wen-Chiao HO ,  Ching-Hung Chang ,  Chung-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： H03M13/05 ,  G06F11/07 ,  H03M13/29 ,  G06F11/10

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。

公开(公告)号：US08891313B2

公开(公告)日：2014-11-18

申请号：US12907263

申请日：2010-10-19

申请人： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

发明人： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC分类号： G11C16/28 ,  G11C7/12 ,  G11C7/10 ,  G11C7/08 ,  G11C7/18

CPC分类号： G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.

摘要翻译： 存储器件的读操作。 响应于指示从不同页面读取数据的输入地址，所选择的字线，第一和第二全局位线和所选择的第一位线组被预充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线被保持预充电。 产生流过所选字线的第二单元电流。 产生第二个参考电流。 基于第二单元电流和第二参考电流来读取第二半页数据。