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公开(公告)号：US08386881B2
公开(公告)日：2013-02-26
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
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公开(公告)号：US08327065B2
公开(公告)日：2012-12-04
申请号：US12566236
申请日：2009-09-24
申请人： Hirokuni Yano , Shinichi Kanno
发明人： Hirokuni Yano , Shinichi Kanno
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7202
摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.
摘要翻译： 根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。 存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。 当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。
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公开(公告)号：US20120246383A1
公开(公告)日：2012-09-27
申请号：US13217461
申请日：2011-08-25
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/1068
摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。
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公开(公告)号：US20120226957A1
公开(公告)日：2012-09-06
申请号：US13218812
申请日：2011-08-26
CPC分类号： G06F11/1048
摘要： According to an embodiment of a controller, a bit string manipulating unit manipulates a bit string of manipulation target data based on a predetermined rule. A special data setting unit generates a magic number based on a special data setting request from a host interface, obtains an error detecting code for the magic number, and sends the magic number and the error detecting code as manipulation target data to the bit string manipulating unit to obtain a manipulated manipulation target data. The special data setting unit also extracts logical block address information from the special data setting request, and instructs an access unit to write the magic number in the manipulated manipulation target data to a user data storage area and to write the error detecting code in the manipulated manipulation target data to a redundant area in a storage area located by the logical block address information.
摘要翻译： 根据控制器的实施例，位串操作单元基于预定规则来操纵操作对象数据的位串。 专用数据设定部基于来自主机接口的特殊数据设定请求生成魔术数，获得魔术数的错误检测码，将魔术号码和错误检测码作为操作对象数据发送到位串操作 单位以获得操纵的操纵目标数据。 特殊数据设定单元还从特殊数据设定请求中提取逻辑块地址信息，并指示访问单元将操作操作目标数据中的魔术数字写入用户数据存储区域，并将错误检测码写入被操纵的 将操作对象数据提供给由逻辑块地址信息定位的存储区域中的冗余区域。
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公开(公告)号：US20120072644A1
公开(公告)日：2012-03-22
申请号：US13037970
申请日：2011-03-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译： 根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。 作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。 第一表包括指定第二表条目的信息或指定第三表条目的信息。 半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。
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公开(公告)号：US20110231624A1
公开(公告)日：2011-09-22
申请号：US12883796
申请日：2010-09-16
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/16 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
摘要： According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
摘要翻译： 根据一个实施例，写指令单元指示数据存取单元在由第一物理地址指示的数据存储单元的存储区中写入对象数据，指示管理信息访问单元更新地址转换信息，以及 指示第一个访问单元更新第一个物理地址。 压缩单元提取压缩对象数据的物理地址，指示数据存取单元读取存储在由物理地址指示的数据存储单元的存储区域中的压缩对象数据，指示数据存取单元写入压缩对象数据 在由第二物理地址指示的数据存储单元的存储区域中，指示管理信息存取单元更新地址转换信息，并指示第二存取单元更新第二物理地址。
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公开(公告)号：US07644298B2
公开(公告)日：2010-01-05
申请号：US11819449
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
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公开(公告)号：US20090327802A1
公开(公告)日：2009-12-31
申请号：US12398608
申请日：2009-03-05
IPC分类号： G06F11/20
CPC分类号： G06F11/108 , G06F11/1068
摘要： When data in one semiconductor memory device is corrupted during a padding process by a padding unit and the data cannot be recovered even by using an error correcting code for correcting a data error, a storage control device issues a data recovery request to a data recovery device. The data recovery device reads the data from other semiconductor memory device in response to the data recovery request to recover the data, and returns a recovery result to the padding unit in the storage control device to perform the padding process.
摘要翻译： 当一个半导体存储器件中的数据在填补单元的填充处理期间被破坏时，即使通过使用用于校正数据错误的纠错码也不能恢复数据，存储控制装置向数据恢复装置发出数据恢复请求 。 数据恢复装置响应于数据恢复请求从其他半导体存储装置读取数据以恢复数据，并将恢复结果返回到存储控制装置中的填充单元以执行填充处理。
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公开(公告)号：US20090327604A1
公开(公告)日：2009-12-31
申请号：US12396006
申请日：2009-03-02
IPC分类号： G06F12/06
CPC分类号： G06F3/0656 , G06F3/0614 , G06F3/0688
摘要： A size storage unit stores therein a block size of a memory element. A buffering unit executes buffer processing configured to store data received from a RAID (Redundant Arrays of Inexpensive/Independent Disks) controller into a buffer, and to write the data stored in the buffer into the memory element. A stripe-size receiving unit receives a stripe size that indicates a size of a unit of access at time of access to the memory element by the RAID controller. Writing processing is configured to write data received from the RAID controller into the memory element without executing the buffer processing by the buffering unit, when the stripe size is n times of the block size (n is a positive integer).
摘要翻译： 大小存储单元存储存储元件的块大小。 缓冲单元执行缓冲处理，其被配置为将从RAID（廉价/独立磁盘的冗余阵列）控制器接收的数据存储到缓冲器中，并且将存储在缓冲器中的数据写入存储器元件。 条形尺寸接收单元接收指示由RAID控制器访问存储器元件时的访问单元的大小的条带大小。 写入处理被配置为当条带大小是块大小的n倍（n为正整数）时，将从RAID控制器接收的数据写入存储元件，而不执行缓冲单元的缓冲器处理。
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120.发明授权Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效逻辑电路系统和可编程逻辑电路的工作电压变化方法公开(公告)号：US07461279B2
公开(公告)日：2008-12-02
申请号：US11831722
申请日：2007-07-31
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system, having a programmable logic circuit including a circuit configuration including a first set of plural unit circuits and that is reconfigurable during operation, a circuit configuration information supplier configured to supply circuit configuration information about a second set of plural unit circuits to said programmable logic circuit, a change controller configured to change the circuit configuration of said programmable logic circuit from said first set of said plural unit circuits to said second set of said plural unit circuits based on said circuit configuration information, an operation time measurer configured to measure operation times of said first and second set of plural unit circuits, and a clock-and-voltage supplier configured to use said measured operation times to change from a first frequency and voltage value corresponding to said first set to a second frequency and voltage value corresponding to said second set, and to supply a clock signal having said second frequency and voltage value to said programmable logic circuit, thereby varying a programmable logic circuit frequency and voltage value in accordance with variations in said operation times.
摘要翻译： 一种逻辑电路系统，具有可编程逻辑电路，该可编程逻辑电路包括电路配置，该电路配置包括第一组多个单元电路，并且可在运行期间重新配置;电路配置信息提供器，被配置为将电路配置信息提供给所述多个单元电路的第二组 可编程逻辑电路，变更控制器，被配置为基于所述电路配置信息将所述可编程逻辑电路的电路配置从所述多个单元电路的所述第一组改变为所述多个单元电路的所述第二组;操作时间测量器， 所述第一和第二组多个单位电路的操作时间以及被配置为使用所述测量的操作时间从对应于所述第一组的第一频率和电压值改变为对应于第二频率和电压值的时钟和电压供应器 到第二组，并提供一个时钟信号 将所述第二频率和电压值表示为所述可编程逻辑电路，从而根据所述操作时间的变化来改变可编程逻辑电路的频率和电压值。
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