公开(公告)号：US20120311770A1

公开(公告)日：2012-12-13

申请号：US13578843

申请日：2011-02-17

申请人： Kaiyo Nakajima ,  Haruki Toda ,  Yoshikazu Tanaka

发明人： Kaiyo Nakajima ,  Haruki Toda ,  Yoshikazu Tanaka

IPC分类号： A41B9/00

CPC分类号： A61F13/49011 ,  A61F13/49466 ,  A61F13/5116 ,  A61F13/513 ,  A61F2013/00404 ,  A61F2013/15024 ,  A61F2013/15154 ,  A61F2013/51182 ,  A61F2013/51316

摘要： A disposable wearing article has a skin-contactable sheet moveable relative to a chassis. The chassis includes an inner sheet, an outer sheet and a liquid-absorbent panel interposed between these inner and outer sheets. The absorbent panel lies at least in the crotch region and extends into the front and rear waist regions in the longitudinal direction. In the rear waist region, a skin-contactable sheet adapted to come in contact with the wearer's skin is attached to the inner surface of the inner sheet. The skin-contactable sheet has front and rear ends extending in the transverse direction and lateral portions extending in the longitudinal direction and only the lateral portions are bonded to the inner sheet.

摘要翻译： 一次性穿着物品具有可相对于底盘移动的皮肤接触片材。 底盘包括内片，外片和介于这些内片和外片之间的吸液性片。 吸收性面板至少位于裆下区域中并且在纵向方向上延伸到前后腰部区域。 在后腰部区域中，与皮肤接触的皮肤接触片附着到内片的内表面。 皮肤接触片具有在横向方向上延伸的前端和后端以及在纵向方向上延伸的侧向部分，并且只有侧部结合到内片。

公开(公告)号：US08269207B2

公开(公告)日：2012-09-18

申请号：US13099735

申请日：2011-05-03

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： H01L29/02

CPC分类号： G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

摘要翻译： 相变存储器件具有彼此平行延伸的多个第一布线WL，多个第二布线BL布置成与第一布线WL交叉而被分离或隔离，并且存储单元MC 被布置在第一布线WL和第二布线BL的各交叉点，并且每个布线的一端连接到第一布线WL，另一端连接到第二布线BL。 存储单元MC具有可变电阻元件VR，其存储由于其结晶态和非晶态之间的相变而确定的电阻值和与可变电阻元件VR串联连接的肖特基二极管SD的信息。

公开(公告)号：US20120008372A1

公开(公告)日：2012-01-12

申请号：US13237500

申请日：2011-09-20

申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US20110239091A1

公开(公告)日：2011-09-29

申请号：US13011318

申请日：2011-01-21

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F11/10

CPC分类号： H03M13/15 ,  H03M13/138 ,  H03M13/1515 ,  H03M13/152

摘要： A memory system according to the embodiment comprises a p-adic number converter unit operative to convert δ-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.

摘要翻译： 根据实施例的存储器系统包括一个对数转换器单元，用于将δ位，h位符号转换成一个k位，p-adic数据字（p是3或更多的素数）; 编码器单元，用于从p-adic数据字生成由素数p的残余字段Zp组成的代码C; 存储单元，用于将代码C存储为写入数据; 误差校正单元，用于执行使用从读取数据Y生成的校正子S的操作，用于对读取数据Y进行纠错以再生代码C; 解码器单元，用于逆向转换代码C以再生p-adic数据字; 以及二进制转换器单元，用于将数据字转换为二进制数，以再生二进制数据D.

公开(公告)号：US07989794B2

公开(公告)日：2011-08-02

申请号：US12820996

申请日：2010-06-22

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： H01L29/02

CPC分类号： G11C8/14 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147

摘要： A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of which serves as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.

摘要翻译： 一种电阻变化存储装置，包括基板，形成在基板上方彼此绝缘的第一和第二布线，以及设置在第一和第二布线之间的存储单元，其中存储单元包括：可变电阻元件，用于存储为 信息电阻值; 和与可变电阻元件串联连接的肖特基二极管。 可变电阻元件具有：由包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的复合化合物形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个用作写入或擦除模式的阳离子源，用于将阳离子供应到要容纳在其中的腔室位置的记录层。

公开(公告)号：US07890843B2

公开(公告)日：2011-02-15

申请号：US11674342

申请日：2007-02-13

申请人： Haruki Toda ,  Toshiaki Edahiro

发明人： Haruki Toda ,  Toshiaki Edahiro

IPC分类号： H03M13/00

CPC分类号： G06F11/1068 ,  G11C16/0483

摘要： A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.

摘要翻译： 存储装置包括具有Galois域GF（2n）上的纠错码的错误检测和校正系统，其具有被配置为以模2n-1执行加法/减法的操作电路，其中所述操作电路包括第一和第二操作部分 用于以模M和模N执行加法/减法（其中，M和N是整数，它们通过分解2n-1而获得），第一和第二操作部分用于同时执行加法/减法 彼此并联，以模2n-1输出加法/减法的运算结果，并且其中第一和第二操作部分各自包括加法器电路。

公开(公告)号：US20100328988A1

公开(公告)日：2010-12-30

申请号：US12677017

申请日：2008-09-09

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

摘要翻译： 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US07859885B2

公开(公告)日：2010-12-28

申请号：US11970154

申请日：2008-01-07

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C11/36 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.

摘要翻译： 相变存储器件包括衬底，堆叠在衬底上的多个单元阵列，每个单元阵列包括多个存储器单元的矩阵布局，每个存储器单元作为数据存储为可由相变所确定的电阻值，写入 电路，被配置为以多个单元阵列中的两个相邻存储单元构成的对单元，以将该单元格中的一个写入高电阻值状态，并将另一个单元写入低电阻值状态;以及 读取电路被配置为读取对单元的互补电阻值状态作为一位数据。

公开(公告)号：US07826249B2

公开(公告)日：2010-11-02

申请号：US12559178

申请日：2009-09-14

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

摘要： A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.

摘要翻译： 可编程电阻存储器件包括半导体衬底，至少一个单元阵列，其中存在存储单元布置在半导体衬底上方。 每个存储单元具有可编程电阻元件和存取元件的堆叠结构，可编程电阻元件存储由于电压施加的极性以非易失性方式而确定的高电阻状态或低电阻状态。 存取元件在与选择状态相同的10倍以上的一定电压范围内处于断开状态的电阻值。 读/写电路形成在半导体衬底上，作为用于与单元阵列通信的数据读取和数据写入的单元阵列。

公开(公告)号：US07706167B2

公开(公告)日：2010-04-27

申请号：US11761808

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/36 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.

摘要翻译： 一种电阻变化存储器件，包括：衬底; 单元阵列堆叠在其上，每个包括存储单元的矩阵布局; 写入电路，被配置为写入由两个相邻存储器单元构成的对单元; 以及读取电路，被配置为读取所述对单元的互补电阻值状态作为数据的一位，其中所述存储单元包括用于存储作为信息电阻值的可变电阻元件。 可变电阻元件具有：由包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的复合化合物形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在其中的腔室位置的记录层。