公开(公告)号：US20100328988A1

公开(公告)日：2010-12-30

申请号：US12677017

申请日：2008-09-09

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

摘要翻译： 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US08259489B2

公开(公告)日：2012-09-04

申请号：US12677017

申请日：2008-09-09

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

摘要翻译： 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US08400816B2

公开(公告)日：2013-03-19

申请号：US13237500

申请日：2011-09-20

申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US08031508B2

公开(公告)日：2011-10-04

申请号：US12266879

申请日：2008-11-07

申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US20120008372A1

公开(公告)日：2012-01-12

申请号：US13237500

申请日：2011-09-20

申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US08687406B2

公开(公告)日：2014-04-01

申请号：US13597740

申请日：2012-08-29

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/73

摘要： According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.

摘要翻译： 根据实施例，半导体存储器件包括：配置有多个存储单元垫的存储单元阵列，所述存储单元阵列包括多个第一行，第二行和存储单元，并且存储单元阵列被堆叠 第一和第二行由每个存储单元垫交替共享; 和外围电路。 每个存储单元具有可变电阻特性和电流整流特性。 从所有存储器单元的阳极到阴极的取向是相同的。 外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路，并且向另一条线路电压施加。

公开(公告)号：US20140009997A1

公开(公告)日：2014-01-09

申请号：US14005149

申请日：2012-03-07

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C13/00

CPC分类号： G11C13/003 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/115

摘要： A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，所述存储单元阵列包括存储单元层，所述存储单元层包含多个用于根据不同电阻状态存储数据的存储单元; 以及访问电路，其操作以访问所述存储单元，所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态，并且从所述第二电阻状态改变所述电阻状态 在施加第二极性的电压的情况下，所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行，并且使所述第一和第 连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。

公开(公告)号：US08537595B2

公开(公告)日：2013-09-17

申请号：US13231687

申请日：2011-09-13

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C13/02

CPC分类号： G11C8/12 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.

摘要翻译： 一种电阻变化存储器件包括：具有层叠在其上的多层垫的单元阵列，每个垫具有彼此相交的字线和位线以及布置在其交叉处的电阻变化型存储单元，每个垫还具有 其中参考单元和连接到参考单元的参考位线，参考单元设置为一定电阻值的状态; 选择电路，被配置为选择单元阵列的每个矩阵中的字线，并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器，被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。

公开(公告)号：US08315082B2

公开(公告)日：2012-11-20

申请号：US13446137

申请日：2012-04-13

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/56 ,  G11C13/0033 ,  G11C13/004 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2213/72

摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.

摘要翻译： 电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路， 在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

公开(公告)号：US08237143B2

公开(公告)日：2012-08-07

申请号：US13217493

申请日：2011-08-25

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： H01L29/02

CPC分类号： G11C13/0004 ,  G11C5/02 ,  G11C7/18 ,  G11C13/0007 ,  G11C2211/4013 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.

摘要翻译： 存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。