公开(公告)号：US09355945B1

公开(公告)日：2016-05-31

申请号：US14843967

申请日：2015-09-02

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： You Ge ,  Meng Kong Lye ,  Zhijie Wang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A packaged semiconductor device has a top and a bottom and includes a lead frame, a die, and an encapsulant that encapsulates the die and most of the lead frame. The lead frame includes a die pad on which the die is mounted, leads electrically connected to the die such as with bond wires, and die pad extensions that fan out from the die pad. Each die-pad extension has a proximal segment and a distal segment. The distal segments are interleaved with the leads. The bottoms of the die pad and the proximal segments of the extensions may be exposed at the bottom of the device. The top of the device may have notches corresponding to the extensions and portions of the distal segments may be exposed and bent into corresponding ones of the notches at the top of the device.

Abstract translation: 封装的半导体器件具有顶部和底部，并且包括引线框架，管芯和密封剂，其封装管芯和引线框架的大部分。 引线框架包括其上安装有管芯的管芯焊盘，引线例如用接合线电连接到管芯，以及从管芯焊盘扇出的管芯焊盘延伸部。 每个模垫延伸部具有近端段和远端段。 远端段与引线交错。 管芯焊盘的底部和延伸部分的近端段可能暴露在设备的底部。 装置的顶部可以具有对应于延伸部的切口，并且远端部分的部分可以暴露并弯曲成在装置的顶部的相应的凹口中。

公开(公告)号：US20160150164A1

公开(公告)日：2016-05-26

申请号：US14551615

申请日：2014-11-24

Applicant: MICHAEL ANDREAS STAUDENMAIER ,  STEPHAN HERRMANN ,  ROBERT CRISTIAN KRUTSCH

Inventor： MICHAEL ANDREAS STAUDENMAIER ,  STEPHAN HERRMANN ,  ROBERT CRISTIAN KRUTSCH

IPC: H04N5/262 ,  B60R1/00 ,  H04N5/265 ,  H04N5/247 ,  H04N5/232

CPC classification number: H04N5/2628 ,  B60R1/00 ,  B60R2300/105 ,  B60R2300/303 ,  B60R2300/306 ,  H04N5/23229 ,  H04N5/23238 ,  H04N5/247 ,  H04N5/265

Abstract: A system controller controls a multi-camera view system for displaying an output image on a display. The output image is a view from a selected viewpoint. The system controller comprises an image resizing unit, a memory, and a processing unit. The image resizing unit receives the at least two input images captured by at least two cameras and is arranged to output to the memory at least two resized images, corresponding to the at least two input images, respectively. The image resizing unit resizes the at least two input images based on the selected viewpoint. The memory stores the two resized images. The processing unit is coupled to the memory and generates the output image from the at least two resized images.

Abstract translation: 系统控制器控制用于在显示器上显示输出图像的多摄像机视图系统。 输出图像是从所选视点的视图。 系统控制器包括图像调整单元，存储器和处理单元。 图像调整单元接收由至少两个摄像机捕获的至少两个输入图像，并且被布置为分别对应于至少两个输入图像的至少两个调整大小的图像输出到存储器。 图像调整单元基于所选择的视点来调整至少两个输入图像的大小。 存储器存储两个调整大小的图像。 处理单元耦合到存储器并且从至少两个调整大小的图像生成输出图像。

公开(公告)号：US20160149934A1

公开(公告)日：2016-05-26

申请号：US14898779

申请日：2013-07-18

Applicant: Juergen FRANK ,  Michael STAUDEN-MAIER ,  Manfred THANNER ,  FREESCALE SEMICONDUCTOR, INC.

Inventor： JUERGEN FRANK ,  MICHAEL STAUDENMAIER ,  MANFRED THANNER

IPC: H04L29/06

CPC classification number: H04L63/1416 ,  G06F21/606 ,  H04L12/40032 ,  H04L12/40169 ,  H04L63/10 ,  H04L63/12 ,  H04L63/1466 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A communication apparatus for preventing the broadcasting of unauthorised messages on a broadcast bus network, the communication apparatus comprising: a first memory adapted to store first information; a second memory adapted to store second information; a monitoring unit adapted to: monitor the bus for processing messages being broadcasted on the bus, and output a third information and fourth information a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, a message destroyer adapted to: when: the first information matches with the third information, and the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.

Abstract translation: 一种用于防止在广播总线网络上广播未经授权的消息的通信装置，所述通信装置包括：适于存储第一信息的第一存储器; 适于存储第二信息的第二存储器; 监视单元，适于：监视总线，以处理在总线上广播的消息，并输出第三信息和第四信息;比较单元，适于将第一信息与第三信息和第二信息与第四信息进行比较; 以及消息驱逐器，其适于：何时：所述第一信息与所述第三信息匹配，并且所述第二信息与所述第四信息不匹配，导致当前消息的主体在当前消息在 总线。

公开(公告)号：US20160149781A1

公开(公告)日：2016-05-26

申请号：US14606424

申请日：2015-01-27

Applicant: ALEXANDRU BOGDAN ANDREESCU

Inventor： ALEXANDRU BOGDAN ANDREESCU

IPC: H04L12/26

CPC classification number: H04L43/0829 ,  H04L41/142

Abstract: A first network node for communicating with a second network node over a first communication network is described. The second network node is arranged to communicate over the first communication network in a first part of a communication period and arranged to not communicate over the first communication network in a second part of the communication period. The first network node has a send unit for sending data formatted in data packets to the second network node, a statistics unit arranged for determining a success statistics, an availability estimator for deriving an availability estimation from the success statistics, and a send controller arranged to control the send unit in dependence on the availability estimation. Also described is a communication system, a method of estimating availability of a second network node, a method of communicating by a first network node, and an associated computer program product.

Abstract translation: 描述了用于通过第一通信网络与第二网络节点进行通信的第一网络节点。 第二网络节点被布置成在通信时段的第一部分中通过第一通信网络进行通信，并且被布置为在通信时段的第二部分中不通过第一通信网络进行通信。 第一网络节点具有用于将数据分组格式化的数据发送到第二网络节点的发送单元，布置成用于确定成功统计的统计单元，用于从成功统计导出可用性估计的可用性估计器，以及发送控制器， 根据可用性估计来控制发送单元。 还描述了通信系统，估计第二网络节点的可用性的方法，由第一网络节点进行通信的方法以及相关联的计算机程序产品。

公开(公告)号：US09350381B1

公开(公告)日：2016-05-24

申请号：US14715022

申请日：2015-05-18

Applicant: Olivier Vincent Doare ,  Rex Kenton Hales

Inventor： Olivier Vincent Doare ,  Rex Kenton Hales

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/378 ,  H03M3/464

Abstract: The circuit generates an analog output signal which may be used to test a sigma-delta ADC. A digital waveform generator supplies a digital signal to a DAC to convert the digital signal into an analog signal. A filter filters the analog signal to obtain the analog output signal. The DAC is a DAC of a sigma-delta ADC and the filter comprises a filter of the sigma/delta ADC. A multiplexer 34 supplies the digital signal to the DAC in a generator mode wherein the circuit converts the digital signal into the analog output signal using the part of the sigma-delta ADC, or to supply a quantized analog output signal to the DAC in normal mode wherein the sigma-delta ADC converts its analog input signal into the quantized analog output signal.

Abstract translation: 该电路产生可用于测试Σ-ΔADC的模拟输出信号。 数字波形发生器将数字信号提供给DAC以将数字信号转换为模拟信号。 滤波器滤除模拟信号以获得模拟输出信号。 DAC是Σ-ΔADC的DAC，滤波器包括Σ/ΔADC滤波器。 多路复用器34以发生器模式将数字信号提供给DAC，其中电路使用Σ-ΔADC的一部分将数字信号转换成模拟输出信号，或者以正常模式将量化的模拟输出信号提供给DAC 其中Σ-ΔADC将其模拟输入信号转换成量化的模拟输出信号。

公开(公告)号：US09350296B1

公开(公告)日：2016-05-24

申请号：US14604428

申请日：2015-01-23

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Khurram Waheed ,  Chris N. Stoll

IPC: H03C3/09 ,  H03C3/04

CPC classification number: H03C3/0991 ,  H03C3/04 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C2200/0041 ,  H03C2200/005

Abstract: The present disclosure provides for a phase-locked loop (PLL) that includes a high-port calibration control module configured to calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency, and capture a positive frequency value of the output signal after a first accumulation time period. The high-port calibration control module is also configured to calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency, capture a negative frequency value of the output signal after a second accumulation time period, and calculate a calibration scale factor based on a difference between the positive and negative frequency values.

Abstract translation: 本公开提供了一种锁相环（PLL），其包括高端口校准控制模块，该高端口校准控制模块被配置为将压控振荡器（VCO）的输入调制值校准为第一调制值，其导致输出信号 VCO具有从初始输出频率的正频率变化，并且在第一累积时间段之后捕获输出信号的正频率值。 高端口校准控制模块还被配置为将VCO的输入调制值校准为第二调制值，其导致输出信号具有来自初始输出频率的负频率变化，捕获输出信号的负频率值 在第二累积时间段之后，并且基于正和负频率值之间的差计算校准比例因子。

公开(公告)号：US09346670B2

公开(公告)日：2016-05-24

申请号：US14958966

申请日：2015-12-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Aaron A. Geisberger ,  Margaret L. Kniffin

IPC: B81C1/00 ,  H01L21/76 ,  H01L41/113

CPC classification number: B81C1/00658 ,  B81B3/0027 ,  B81B3/0078 ,  B81B2201/025 ,  B81C1/0015 ,  G01C19/574 ,  G01P15/125 ,  G01P2015/0831 ,  H01L21/76 ,  H01L41/113 ,  H01L41/1136

Abstract: A MEMS device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The MEMS device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. The second sense electrode is spaced apart from the first portion of the sense mass in a direction perpendicular to a surface of the substrate, and the second portion of the sense mass is spaced apart from the first sense electrode in the same direction. A junction is formed between the first and second portions of the sense mass so that they are coupled together and move concurrently in response to an imposed force.

Abstract translation: MEMS器件包括第一感测电极和形成在第一结构层中的感测质量的第一部分，其中第一感测电极与衬底固定耦合，并且感测质量块的第一部分悬挂在衬底上。 MEMS器件还包括形成在第二结构层中的第二感测电极和感测质量的第二部分。 第二感测电极在垂直于衬底的表面的方向上与感测质量块的第一部分间隔开，并且感测质量块的第二部分在相同方向上与第一感测电极间隔开。 在感测体的第一和第二部分之间形成接合点，使得它们耦合在一起并且响应于施加的力同时移动。

公开(公告)号：US20160142458A1

公开(公告)日：2016-05-19

申请号：US14899132

申请日：2013-07-04

Applicant: ROY SHOR ,  ORI GOREN ,  AVRAHAM HORN ,  AVRAHAM RABINOVICH

Inventor： ROY SHOR ,  ORI GOREN ,  AVRAHAM HORN ,  AVRAHAM RABINOVICH

IPC: H04L29/06

CPC classification number: H04L65/60 ,  H04L29/08 ,  H04L29/10 ,  H04W76/00 ,  H04W88/085

Abstract: Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

Abstract translation: 在移动通信系统中的基站中的无线电单元之间的接口使用普通的公共无线电接口CPRI来流式化布置在车道中的IQ数据样本。 现在另外使用单独的串行接口sRIO来传送分组中排列的所选数据样本，所选择的样本对应于通过公共无线电接口在其它无线电单元之间流动的所选择的通道。 在无线电单元中，所选择的数据样本被布置成要经由串行接口发送的分组，反之亦然，经由串行接口接收的分组中排列的所选数据样本被布置在通道中。 耦合到CPRI的系统定时器产生用于控制sRIO接口的时基，以使其同步。 有利的是，使用基于分组的串行接口来扩展流式CPRI接口的数据样本传送容量。

公开(公告)号：US09344180B2

公开(公告)日：2016-05-17

申请号：US14528567

申请日：2014-10-30

Applicant: Razvan-Tudor Stanescu ,  Florin-Catalin Toma

Inventor： Razvan-Tudor Stanescu ,  Florin-Catalin Toma

IPC: H04Q11/00 ,  H04L12/50 ,  H04B7/08 ,  H04B1/7156 ,  H04B7/12 ,  H04B17/29

CPC classification number: H04B7/0814 ,  H04B1/7156 ,  H04B7/0802 ,  H04B7/12 ,  H04B17/29 ,  H04B2001/71563

Abstract: An antenna-diversity receiver receives data units from a transmitter in a frequency-hopping communication system. The frequency-hopping system has a channel set comprising of multiple channels, each having its own frequency range. The channel set comprises a set of multiple advertising channels and a set of multiple data channels. The receiver comprises an antenna set of multiple antennas.The transmitter has an advertising mode in which the transmitter transmits an advertising signal and switches from one advertising channel to another advertising channel in accordance with a sequence of advertising intervals, each advertising interval comprising an advertising packet.The receiver has an antenna sampling mode in which the receiver receives, successively for each combination of antenna and advertising channel, advertising packets. The receiver determines a corresponding signal quality value and selects, for each data channel, an antenna from the antenna set on the basis of the determined signal quality values.

Abstract translation: 天线分集接收机在跳频通信系统中从发射机接收数据单元。 跳频系统具有由多个信道组成的信道集合，每个信道具有其自己的频率范围。 信道集合包括一组多个广告信道和一组多个数据信道。 接收机包括多个天线的天线组。 发射机具有广告模式，其中发射机根据广告间隔的顺序发送广告信号并从一个广告信道切换到另一个广告信道，每个广告间隔包括广告包。 接收机具有天线采样模式，其中接收机连续地针对天线和广告信道的每个组合接收广告分组。 接收机确定相应的信号质量值，并且基于所确定的信号质量值，从每个数据信道选择来自天线组的天线。

公开(公告)号：US09343966B1

公开(公告)日：2016-05-17

申请号：US14635891

申请日：2015-03-02

Applicant: Nishant Singh Thakur

Inventor： Nishant Singh Thakur

IPC: G05F3/16 ,  H02M3/156

CPC classification number: H02M3/156

Abstract: A voltage switching system for an integrated circuit (IC) operable in first and second operational modes includes a handover module, first and second voltage regulators, a switch driver, a transistor, and a comparator. When the IC transitions between modes, the handover module receives ramp control and hand-over start signals, generates comparator and bandwidth control signals based on the hand-over start signal and a ramp signal based on the ramp control signal. The switch driver generates a power control signal based on the comparator control signal and a gate input signal based on the ramp signal. The comparator compares first and second voltage signals based on the power control signal and generates a hand-over complete signal. The handover module generates a final hand-over complete signal based on the hand-over complete signal, indicative of completion of transition between the first and second operational modes.

Abstract translation: 用于在第一和第二操作模式中可操作的集成电路（IC）的电压切换系统包括切换模块，第一和第二稳压器，开关驱动器，晶体管和比较器。 当IC在模式之间转换时，切换模块接收斜坡控制和切换启动信号，基于切换起始信号和基于斜坡控制信号的斜坡信号产生比较器和带宽控制信号。 开关驱动器基于比较器控制信号和基于斜坡信号的栅极输入信号产生功率控制信号。 比较器基于功率控制信号比较第一和第二电压信号，并生成切换完成信号。 切换模块基于切换完成信号产生指示完成第一和第二操作模式之间的转换的最终切换完成信号。