公开(公告)号：US10910371B2

公开(公告)日：2021-02-02

申请号：US16535778

申请日：2019-08-08

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L27/088 ,  H01L21/82 ,  H01L21/765 ,  H01L23/34 ,  H01L21/762 ,  H01L21/66 ,  G01R31/28 ,  H01L21/8234 ,  H01L27/092

摘要： A method for detecting heat generated by a semiconductor device including a first MOS device and an active device on a substrate is provided. The method includes obtaining a first curve of a performance parameter of the first MOS device as a function of temperature when the active device is not operating, obtaining a second curve of the performance parameter of the first MOS device as a function of temperature when the active device is operating, and obtaining a heat generating condition of the active device according to a degree of deviation between the first curve and the second curve.

公开(公告)号：US10910332B2

公开(公告)日：2021-02-02

申请号：US16530360

申请日：2019-08-02

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： You Wu ,  Jun Zhu

IPC分类号： H01L23/12 ,  H01L23/00 ,  H01L27/146

摘要： A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.

公开(公告)号：US20210028007A1

公开(公告)日：2021-01-28

申请号：US16935561

申请日：2020-07-22

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shiliang JI ,  Bo SU ,  Haiyang ZHANG

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/3213

摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

公开(公告)号：US20210013313A1

公开(公告)日：2021-01-14

申请号：US16922730

申请日：2020-07-07

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan WANG

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66

摘要： A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove.

公开(公告)号：US20210013215A1

公开(公告)日：2021-01-14

申请号：US17032820

申请日：2020-09-25

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong LI

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

摘要： An SRAM (static random access memory) includes a semiconductor substrate; a plurality of PD transistors, each including a first fin structure formed on the semiconductor substrate, a PD gate structure formed across the first fin structure and covering a portion of a top and sidewall surfaces of the first fin structure, and a first source/drain doped layer formed in the first fin structure on both sides of the PD gate structure; a plurality of adjacent transistors, each including a second fin structure formed on the semiconductor substrate and a second source/drain doped layer formed in the second fin structure; an isolation layer, formed on the semiconductor substrate; a fin sidewall film, formed on the isolation layer and covering sidewall surfaces of each PD gate structure; and a first PD dielectric layer, formed on the isolation layer and covering sidewall surfaces of the first source/drain doped layer.

公开(公告)号：US20210013030A1

公开(公告)日：2021-01-14

申请号：US16924976

申请日：2020-07-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Hui QU

IPC分类号： H01L21/02 ,  H01L21/67

摘要： A method for processing a product layer includes providing a dielectric layer over a substrate, etching to remove a portion of the dielectric layer, forming a product layer over the etched dielectric layer, and removing the product layer by providing a dissolving solution and using the dissolving solution to rinse or soak the product layer to dissolve the product layer.

公开(公告)号：US20200381516A1

公开(公告)日：2020-12-03

申请号：US16601847

申请日：2019-10-15

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhaomeng

IPC分类号： H01L29/08 ,  H01L21/768 ,  H01L29/417 ,  H01L21/265 ,  H01L21/266

摘要： The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region. The first doped region and the second doped region surround a contact hole plug in the source-drain doped region, such that the contact hole plug is not easily in direct contact with the source-drain doped region, contact resistance between the contact hole plug and the source-drain doped region is reduced, and the electrical performance of the semiconductor structure is improved.

公开(公告)号：US10825690B2

公开(公告)日：2020-11-03

申请号：US16243297

申请日：2019-01-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Cheng Long Zhang ,  Hai Yang Zhang ,  Yan Wang

IPC分类号： H01L21/308 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

摘要： A semiconductor structure a base substrate and a sidewall spacer layer formed on the base substrate. The sidewall spacer layer includes a plurality of first sidewall spacer layers and a plurality of second sidewall spacer layers spaced apart from each other. At least one sidewall of a second sidewall spacer layer of the plurality of second sidewall spacer layers is formed on a first sidewall spacer layer of the plurality of first sidewall spacer layers. The plurality of first sidewall spacer layers has a thickness greater than the plurality of second sidewall spacer layers, based on a surface of the base substrate. The plurality of first sidewall spacer layers has a material structure different than the plurality of second sidewall spacer layers.

公开(公告)号：US10811513B2

公开(公告)日：2020-10-20

申请号：US16559891

申请日：2019-09-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong Li

IPC分类号： H01L29/66 ,  G11C11/412 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/775

摘要： A vertical tunneling field effect transistor is provided and includes: a semiconductor substrate; a first doped layer on the semiconductor substrate; vertical nanowires on the first doped layer; a second doped layer on a top of each vertical nanowire; an interlayer dielectric layer on the first doped layer, including a cavity between the adjacent vertical nanowires through the interlayer dielectric layer and exposing sidewalls of the adjacent vertical nanowires; a high-K gate dielectric layer in sidewalls and a bottom of each cavity; and a gate electrode layer on the high-K gate dielectric layer to fill each cavity.

公开(公告)号：US10797177B2

公开(公告)日：2020-10-06

申请号：US16417979

申请日：2019-05-21

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong Li

IPC分类号： H01L21/268 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having PMOS and NMOS regions. The PMOS region includes a first region, a first gate structure on the first region, and first source and drain regions on opposite sides of the first gate structure. The NMOS region includes a second region and a second gate structure on the second region. The method also includes introducing a p-type dopant into the first source and drain regions, performing a first annealing, forming second source and drain regions on opposite sides of the second gate structure, introducing an n-type dopant into the second source and drain regions, and performing a second annealing. The method satisfies thermal budget requirements of forming PMOS and NMOS devices, thereby enabling a better diffusion of the p-type dopant into the source and drain regions of the PMOS device without affecting the performance of the NMOS device.