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公开(公告)号：US20230318171A1
公开(公告)日：2023-10-05
申请号：US18194855
申请日：2023-04-03
Inventor： Olivier Ptak , Ouafa Hajji , Georg Kimmich
Abstract: An electronic device includes an electronic chip assembled on a first region of a substrate of the electronic device, a first coating layer of a first coating material covering a surface of the electronic chip facing away from the substrate, and a radiation element of an antenna of the electronic device separated from the substrate by at least a portion of the first coating layer and being offset with respect to the first region of the substrate so that the radiation element does not cover the electronic chip. The radiation element is buried in the first coating layer or is arranged in the first coating layer and partly covered with a protection material.
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公开(公告)号：US20230297126A1
公开(公告)日：2023-09-21
申请号：US18119535
申请日：2023-03-09
Inventor： Alexandre TRAMONI , Florent SIBILLE , Patrick ARNOULD
CPC classification number: G05F1/46 , H04B5/0037
Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.
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公开(公告)号：US11757477B2
公开(公告)日：2023-09-12
申请号：US17187024
申请日：2021-02-26
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Rivoirard , Felix Gauthier
CPC classification number: H04B1/0096 , H03D7/125 , H04W88/06
Abstract: An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.
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公开(公告)号：US11756874B2
公开(公告)日：2023-09-12
申请号：US17945822
申请日：2022-09-15
Inventor： David Auchere , Claire Laporte , Deborah Cogoni , Laurent Schwartz
CPC classification number: H01L23/50 , H01L23/315 , H01L23/3128
Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
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115.发明授权公开(公告)号：US11700174B2
公开(公告)日：2023-07-11
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0803 , H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , G06F21/85
CPC classification number: H04L41/0813 , G06F15/177 , G06F15/17306 , H04L41/0803 , H04L49/109 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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Patent Agency Ranking
116.发明授权公开(公告)号：US11698993B2
公开(公告)日：2023-07-11
申请号：US17161544
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
CPC classification number: G06F21/72 , H04L9/06 , H04L9/0866 , G06F2221/2113
Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.
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公开(公告)号：US11663365B2
公开(公告)日：2023-05-30
申请号：US16928901
申请日：2020-07-14
Inventor： Marc Benveniste , Fabien Journet , Fabrice Marinet
CPC classification number: G06F21/75 , G06F1/08 , G06F3/1238 , G06F21/44 , G06F21/72 , H04L9/3236 , H04L9/3247
Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.
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公开(公告)号：US11641191B2
公开(公告)日：2023-05-02
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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119.发明授权公开(公告)号：US11610025B2
公开(公告)日：2023-03-21
申请号：US17161194
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.
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公开(公告)号：US20230056937A1
公开(公告)日：2023-02-23
申请号：US17881749
申请日：2022-08-05
Inventor： Danika Perrin , Sandrine Nicolas
IPC: H04B1/16
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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