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公开(公告)号：US5793439A
公开(公告)日：1998-08-11
申请号：US803227
申请日：1997-02-20
申请人： Kesatoshi Takeuchi
发明人： Kesatoshi Takeuchi
IPC分类号： G09G1/16 , G09G3/20 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395 , H04N5/44 , H04N5/445 , H04N5/45 , H04N9/64 , H04N9/74
CPC分类号： G09G1/167 , G09G5/14 , G09G5/39 , G09G5/395 , H04N21/4143 , H04N5/44 , H04N5/44504 , H04N5/45 , H04N9/641 , G09G2340/0435 , G09G2340/125 , G09G2360/02 , G09G2360/126 , G09G5/001 , G09G5/008 , G09G5/363 , G09G5/393 , H04N5/4401
摘要： An image control device for use in a computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.
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112.发明授权Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register 失效图形处理器在写入控制寄存器的同时写入预定地址的影子寄存器
公开(公告)号：US5696923A
公开(公告)日：1997-12-09
申请号：US474863
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G06F9/30 , G06F12/02 , G09G5/06 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/395 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F9/30101 , G06F12/0284 , G06F3/14 , G06F3/1438 , G06F9/3879 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.
摘要翻译： 计算机图形系统包括主计算机和图形处理器。 图形处理器包括一个控制寄存器。 当图形处理器向控制寄存器写入时，它同时在本地地址总线上产生一个预定的地址，并将数据提供给与写入控制寄存器的数据相同的本地数据总线上。 连接到主计算机和图形处理器的影子寄存器电路包括影子寄存器和第一和第二地址解码器。 第一地址解码器能够在检测到预定地址时从本地数据总线写入影子寄存器。 当检测到主机地址总线上的预定地址时，第二地址解码器能够经由主机数据总线从影子寄存器读取。 影子寄存器可选地包括多个比特的消息和多个比特的消息，第一和第二地址解码器使能主机计算机和图形处理器之间的消息传递。 影子寄存器电路可选地包括主机中断位和缓冲电路。 如果图形处理器产生主机中断信号或影子寄存器的主机中断位具有预定状态，则缓冲电路向主计算机产生主机中断信号。
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公开(公告)号：US5625386A
公开(公告)日：1997-04-29
申请号：US315653
申请日：1994-09-30
申请人： Brian D. Howard , Robert L. Bailey
发明人： Brian D. Howard , Robert L. Bailey
CPC分类号： G09G5/397 , G06F3/14 , G09G5/391 , G09G2340/10 , G09G2340/12 , G09G2360/126
摘要： A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral access, a display system, a single memory system for storing multiple frame buffers, data buses for transferring image information and a video controller for processing the image information received and for converting CPU addresses into memory addresses for accessing the memory system. The multiple frame buffers stored in the memory system in accordance with the present invention provide either overlay images for a display or separate images for separate displays or both.
摘要翻译： 公开了一种用于交织显示帧缓冲器的方法和装置。 该系统包括提供用于外围设备访问的CPU地址的处理器，显示系统，用于存储多个帧缓冲器的单个存储器系统，用于传送图像信息的数据总线和用于处理接收到的图像信息的视频控制器，以及用于将CPU地址转换成存储器地址 用于访问存储系统。 存储在根据本发明的存储器系统中的多个帧缓冲器提供用于显示器的叠加图像或用于单独显示器或两者的单独图像。
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公开(公告)号：US5610630A
公开(公告)日：1997-03-11
申请号：US584156
申请日：1996-01-11
CPC分类号： G09G5/397 , G06F3/1423 , G09G3/003 , G09G5/14 , G06F3/14 , G09G2340/12 , G09G2340/125 , G09G2360/126
摘要： A graphic display control system performs multi-window display at a workstation or the like. The graphic display control system comprises image display means whose display screen is composed of a plurality of pixels or character sections; at least two image storage means each of which has a storage capacity for one display screen of the image display means; two image selection information storage means which store image selection information for selecting one of the at least two image storage means for one pixel or one character section composing one display screen of the image display means; selection information output means which selects one of the two image selection information storage means and outputs the image selection information stored in the selected image selection information storage means; and image selection output means which selects one of the at least two image storage means for one pixel or one character section on the basis of the image selection information outputted by the selection information output means, and outputs the image information stored at the pixel position or character position corresponding to the selected image storage means to the image display means.
摘要翻译： 图形显示控制系统在工作站等进行多窗口显示。 图形显示控制系统包括图像显示装置，其显示屏幕由多个像素或字符部分组成; 至少两个图像存储装置，每个图像存储装置具有用于图像显示装置的一个显示屏幕的存储容量; 两个图像选择信息存储装置，存储用于选择构成图像显示装置的一个显示屏幕的一个像素或一个字符部分的至少两个图像存储装置中的一个的图像选择信息; 选择信息输出装置，其选择两个图像选择信息存储装置中的一个，并输出存储在所选择的图像选择信息存储装置中的图像选择信息; 以及图像选择输出装置，其基于由选择信息输出装置输出的图像选择信息，为一个像素或一个字符部分选择至少两个图像存储装置中的一个，并输出存储在像素位置处的图像信息或 对应于所选择的图像存储装置的字符位置到图像显示装置。
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公开(公告)号：US5544306A
公开(公告)日：1996-08-06
申请号：US237307
申请日：1994-05-03
CPC分类号： G09G5/39 , G06T15/405 , G06F12/0875 , G09G2340/10 , G09G2360/121 , G09G2360/123 , G09G2360/126
摘要： A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
摘要翻译： 公开了一种帧缓冲器动态随机存取存储器（FBRAM），其实现了Z缓冲图形基元的加速渲染。 FBRAM将读取 - 修改 - 写入事务（如Z缓冲区比较和RBG alpha混合）转换为只写操作。 FBRAM还实现了两级内部像素高速缓存和四路交错帧缓冲器。
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116.发明授权
公开(公告)号：US5426734A
公开(公告)日：1995-06-20
申请号：US170572
申请日：1993-12-20
申请人： Yasushi Nakaoka
发明人： Yasushi Nakaoka
CPC分类号： G09G5/001 , G09G5/39 , G09G5/395 , G09G2360/126
摘要： An apparatus for controlling an image display device such as the CRT includes a dual port memory having a first memory and a second memory. Data may be written into a first memory and read from the first memory at any time. Data is sequentially read from the second memory to provide information for the display. Data is manipulated during a data transfer cycle, a dynamic memory refresh cycle, a memory write cycle and a memory read cycle. Data is transmitted between the first memory and second memory during a data transfer cycle. A cycle reconciliation circuit prioritizes the manner in which the cycles occur giving top priority to the data transfer cycle.
摘要翻译： 用于控制诸如CRT的图像显示装置的装置包括具有第一存储器和第二存储器的双端口存储器。 数据可以被写入第一存储器并随时从第一存储器读取。 依次从第二存储器读取数据以提供用于显示的信息。 在数据传输周期，动态存储器刷新周期，存储器写入周期和存储器读取周期期间操作数据。 在数据传输周期期间，数据在第一存储器和第二存储器之间传送。 循环调节电路优先考虑周期发生的方式给数据传输周期的最高优先级。
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公开(公告)号：US5201037A
公开(公告)日：1993-04-06
申请号：US430952
申请日：1989-10-31
CPC分类号： G09G5/363 , G09G5/393 , G09G2360/126
摘要： A display system uses a dual-port memory having a random access memory part and a serial access memory part as a frame buffer. Display data is transferred from the random access memory part to the serial access memory part in response to a timing signal of the data transfer. Just prior to the timing signal, an access start disable signal is generated, which has an active period being equal to or longer than an access cycle time of drawing data. When the access start disable signal is active, a draw access from a central processing unit, etc. to the dual port memory becomes disable. Further, address bits for a column of the memory are detected to become all zero and a predetermined value, so that the timing of a real time data transfer and the access start disable signal for the real time data transfer can be generated.
摘要翻译： 显示系统使用具有随机存取存储器部分和串行存取存储器部分作为帧缓冲器的双端口存储器。 响应于数据传送的定时信号，显示数据从随机存取存储器部分传送到串行存取存储器部分。 恰好在定时信号之前，生成访问开始禁止信号，其具有等于或长于绘制数据的访问周期时间的活动周期。 当访问启动禁止信号有效时，从中央处理单元等到双端口存储器的绘图访问被禁用。 此外，检测存储器的列的地址位变为全零和预定值，从而可以生成实时数据传送的定时和用于实时数据传送的访问开始禁止信号。
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公开(公告)号：US4994912A
公开(公告)日：1991-02-19
申请号：US314623
申请日：1989-02-23
申请人： Leon Lumelsky , Alan W. Peevers
发明人： Leon Lumelsky , Alan W. Peevers
CPC分类号： G09G5/397 , G09G2340/125 , G09G2360/126
摘要： A method and apparatus for synchronizing two independent rasters, such that a standard TV video and a high resolution computer generated graphics video may each be displayed on a high resolution graphics monitor. This is accomplished utilizing dual frame buffers. A TV frame buffer, comprises a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resolution graphics monitor. A high resolution frame buffer in a computer is utilized to store high resolution graphics which is read out synchronously with the high resolution graphics monitor. A switching mechanism selects which of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion. The computer provides computer data, including high resolution graphics data and audio data to the TV frame buffer, with the graphics data being stored in the on screen portion and the audio data being stored in the off screen portion. The audio data is read out to an audio circuit for replay. The graphics data is combined with the TV video for purposes of windowing.
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公开(公告)号：US4777621A
公开(公告)日：1988-10-11
申请号：US756910
申请日：1985-07-19
CPC分类号： G09G5/001 , G06F13/28 , G09G5/005 , G09G5/393 , G09G5/395 , G09G2360/126 , G09G2360/18
摘要： A video game home computer is implemented in NMOS (n type metal oxide semiconductor) technology with plural microprocessors. Centralized bus architecture and direct memory access (DMA) techniques are employed. A video display generator provides color signal outputs to drive a commercial television receiver display. This display generator receives inputs from both microprocessors and obtains data directly from memory. A bit map of display information is kept in memory, wherein bits of information in memory image the precise screen display for each instance in time. A bit map manipulator circuit performs, under microprocessor direction, logic function manipulation of the bit map data. Access between system components is accomplished via the bus architecture on a priority queue basis. Chip count and chip area is minimized.
摘要翻译： 视频游戏家用计算机在具有多个微处理器的NMOS（n型金属氧化物半导体）技术中实现。 采用集中式总线架构和直接存储器访问（DMA）技术。 视频显示发生器提供彩色信号输出以驱动商业电视接收机显示。 该显示生成器接收来自两个微处理器的输入并直接从存储器获取数据。 显示信息的位图保存在存储器中，其中存储器中的信息位在时间上针对每个实例精确地显示屏幕。 位图操纵器电路在微处理器方向下执行位图数据的逻辑功能操作。 通过基于优先级队列的总线架构来实现系统组件之间的访问。 芯片数量和芯片面积最小化。
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公开(公告)号：US4701865A
公开(公告)日：1987-10-20
申请号：US624175
申请日：1984-06-25
申请人： Robert W. Goodman
发明人： Robert W. Goodman
CPC分类号： G09G5/363 , G09G2360/126
摘要： A video control section for a data processing system for controlling a CRT display is disclosed. The video control section includes a video memory comprising an array of dual port RAMS which is connected through an interface to the system memory bus, a shifter, a palette, a D/A converter, an oscillator section, a timing and synchronizer section and a microprocessor. The microprocessor, which is connected to the system memory bus through an interface, manages the overall operations of the video control section to generate video signals for the CRT display and in addition along with the oscillator section and timing and synchronizer section generates all of the video timing and control signals for the CRT display.
摘要翻译： 公开了一种用于控制CRT显示器的数据处理系统的视频控制部分。 视频控制部分包括视频存储器，其包括通过与系统存储器总线的接口连接的双端口RAMS阵列，移位器，调色板，D / A转换器，振荡器部分，定时和同步器部分以及 微处理器。 通过接口连接到系统存储器总线的微处理器管理视频控制部分的总体操作以产生用于CRT显示器的视频信号，此外，与振荡器部分一起，定时和同步器部分产生所有视频 CRT显示器的定时和控制信号。
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