公开(公告)号：US5515013A

公开(公告)日：1996-05-07

申请号：US423951

申请日：1995-04-18

Applicant: Peter McConnell

Inventor： Peter McConnell

IPC: H03C3/00 ,  H03C3/09 ,  H04L27/12 ,  H03C3/08

CPC classification number: H03C3/0966 ,  H03C3/0941 ,  H03C3/0958

Abstract: A dual port frequency modulator and method for eliminating the undesired affects caused by high port/low port phase differences in a standard dual port frequency modulator. The frequency modulator includes an inverse filter stage coupled to the input of a modulator stage including a first high port processing path for processing high frequency components of a modulation signal and a second low port processing path for processing low frequency components of a modulation signal. The outputs of the high and low paths are coupled to separate ports of a voltage controlled oscillator. The impulse response of the inverse filter is designed to be the inverse of the impulse response of the modulator stage. The filter functions to counter-act the adverse effects caused by the delay difference in the high and low processing paths of the modulator stage such that the overall response of the dual port frequency modulator is significantly improved.

Abstract translation: 双端口频率调制器和方法，用于消除标准双端口频率调制器中由高端口/低端口相位差引起的不期望的影响。 频率调制器包括耦合到调制器级的输入的反相滤波器级，包括用于处理调制信号的高频分量的第一高端口处理路径和用于处理调制信号的低频分量的第二低端处理路径。 高和低路径的输出耦合到压控振荡器的分离端口。 逆滤波器的脉冲响应设计为调制器级的脉冲响应的倒数。 滤波器用于抵消由调制器级的高和低处理路径中的延迟差导致的不利影响，使得双端口频率调制器的总体响应显着提高。

公开(公告)号：US5497509A

公开(公告)日：1996-03-05

申请号：US799579

申请日：1991-11-27

Applicant: Lloyd L. Lautzenhiser ,  Wendell E. Miller

Inventor： Lloyd L. Lautzenhiser ,  Wendell E. Miller

IPC: H03C3/09 ,  H03L7/193 ,  H04B1/26

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/193 ,  H03C2200/0079

Abstract: Signal processing apparatus (410), for processing angularly modulated signals, provides improved sensitivity by reducing both the deviation of the modulation and the frequency of the bandwidth filter below the value calculated by Carson's rule. The signal processing apparatus (410) includes a closed loop (438) and a phase locking oscillator (270, 304, 318, 332, or 392) that is interposed into the closed loop (438). Both the frequency of the angularly modulated signal and the deviations of the angular modulation are reduced in the closed loop (438), and the demodulated output of the angularly modulated signal is produced in a conductor (436) of the closed loop (438). The phase locking oscillator (270, 304, 318, 332, or 392) includes both a forward path (204) and a feedback path (206), and an output frequency of the phase locking oscillator (270, 304, 318, 332, or 392) is phase locked to a reference frequency. The phase locked output frequency, in a conductor (230), is used as an input to the closed loop (438), and a derived signal, in the conductor (436) of the closed loop (438), which is the demodulated output of the angularly modulated signal, is used to vary the phase locked output frequency in the conductor (230). This varying of the phase locked output frequency includes separately modulating a frequency in the forward path (204) and a frequency in the feedback path (206) of the phase locking oscillator (270, 304, 318, 332, or 392). Modulation of frequencies in both paths (204 and 206) is accomplished without changing the reference frequency.

Abstract translation: 用于处理角度调制信号的信号处理装置（410）通过将调制的偏差和带宽滤波器的频率减小到低于由Carson规则计算的值来提供改善的灵敏度。 信号处理装置（410）包括闭环（438）和插入闭环（438）中的锁相振荡器（270,304,318,332或392）。 角度调制信号的频率和角度调制的偏差都在闭环（438）中减小，并且角度调制信号的解调输出在闭环（438）的导体（436）中产生。 相位锁定振荡器（270,304,318,332或392）包括正向路径（204）和反馈路径（206），以及相位锁定振荡器（270,304,318,332或392） 或392）被锁相到参考频率。 在导体（230）中的相位锁定输出频率用作闭环（438）的输入，以及作为解调输出的闭环（438）的导体（436）中的导出信号 使用角度调制信号来改变导体（230）中的锁相输出频率。 这种相位锁定输出频率的变化包括分别调制正向路径（204）中的频率和相位锁定振荡器（270,304,318,332或392）的反馈路径（206）中的频率。 在不改变参考频率的情况下实现两个路径（204和206）中的频率的调制。

公开(公告)号：US5488627A

公开(公告)日：1996-01-30

申请号：US160077

申请日：1993-11-29

Applicant: Keith B. Hardin ,  John T. Fessler ,  Donald R. Bush ,  James J. Booth

Inventor： Keith B. Hardin ,  John T. Fessler ,  Donald R. Bush ,  James J. Booth

IPC: G06F15/78 ,  G06F1/04 ,  H03B29/00 ,  H03C3/09 ,  H03K4/94 ,  H03L7/197 ,  H03D1/04

CPC classification number: H03C3/0966 ,  H03B29/00 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/0805 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

Abstract: A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

公开(公告)号：US5467373A

公开(公告)日：1995-11-14

申请号：US5890

申请日：1993-01-15

Applicant: Hans-Peter Ketterling

Inventor： Hans-Peter Ketterling

IPC: H03C3/09 ,  H04L27/12 ,  H04L27/20 ,  H03D3/24

CPC classification number: H03C3/0966 ,  H03C3/0941 ,  H03C3/095 ,  H04L27/12 ,  H04L27/2017 ,  H04L27/2046 ,  H03C2200/0029 ,  H03C2200/0058 ,  H03C2200/0079

Abstract: For digital transitions from one binary logic level to another by frequency or phase shift of an electric carrier wave the modulation sidebands are reduced by performing each transition by means of several phase steps at small intervals. Equal phase steps at varying intervals are preferred over equal intervals between varying phase steps although both procedures can provide a low-bandwidth transition. This procedure is readily incorporated at low cost in frequency synthesizers. The use of a higher-frequency master oscillator (16) followed by a fixed-ratio frequency divider (17) ahead of a variable-ratio frequency divider (18) makes it easy to shift phase or frequency digitally by small quick steps. Another variable-ratio frequency divider (13) is desirable but not essential in the final PLL between a ultimately controlled oscillator (10) and a loop filter (12) connected to a phase discriminator (11). The discriminator (11) and the two variable-ratio frequency dividers (17, 13) require simultaneous or coordinated initialization (line 20). A binary digital signal produces GMSK modulation by means of a processor in which the divider ratios and their timings and sequence are stored. The steps are small enough for the loop filter to provide adequate bandwidth reduction. Steps each produced by a divisor one unit higher than the divisor which keeps the phase constant for the nominal frequency are produced by one cycle of the reference frequency, which corresponds to a number equal to the overall divisor of cycles of the master oscillator.

Abstract translation: 对于通过电载波的频率或相移从一个二进制逻辑电平到另一个二进制逻辑电平的数字转换，通过以小的间隔通过几个相位步进执行每个转换来减小调制边带。 尽管两个步骤都可以提供低带宽转变，但在变化的相位步长之间的等间隔上优选以不同间隔的相位阶跃。 该方法在频率合成器中以低成本容易地并入。 使用高频主振荡器（16）和可变比分频器（18）之后的固定比分频器（17），使得通过小的快速步进数字地转换相位或频率变得容易。 另一个可变比分频器（13）是期望的，但是在最终控制的振荡器（10）和连接到相位鉴别器（11）的环路滤波器（12）之间的最终PLL中是不必要的。 鉴别器（11）和两个可变比分频器（17,13）需要同时或协调的初始化（线路20）。 二进制数字信号通过其中存储分频比及其定时和序列的处理器产生GMSK调制。 这些步骤足够小，以使环路滤波器提供足够的带宽减少。 除数除以上的除数除了保持标称频率的相位常数的除数之外，由参考频率的一个周期产生，这个周期对应于等于主振荡器周期的总除数的数字。

公开(公告)号：US5461348A

公开(公告)日：1995-10-24

申请号：US325290

申请日：1994-10-27

Applicant: Albert Heuberger ,  Ludwig Wallrapp ,  Dieter Seitzer

Inventor： Albert Heuberger ,  Ludwig Wallrapp ,  Dieter Seitzer

IPC: H03C3/00 ,  H03C3/09

CPC classification number: H03C3/0966 ,  H03C3/0941 ,  H03C3/095 ,  H03C2200/0054 ,  H03C2200/0075

Abstract: A PLL circuit modulatable by a modulation signal having a direct current component has a voltage-controlled main oscillator, a loop divider, a phase comparator and a loop filter. The reference frequency signal for the phase comparator is derived from the modulation signal by a first compensation filter, a voltage-controlled reference oscillator and a reference divider being connected downstream of said first compensation filter. The voltage-controlled main oscillator is controlled by the modulation signal via a second compensation filter followed by a downstream data lowpass.

Abstract translation: PCT No.PCT / EP93 / 00559 Sec。 371日期：1994年10月27日 102（e）日期1994年10月27日PCT 1993年3月11日PCT公布。 公开号WO93 / 22829 日期：1993年11月11日。具有直流分量的调制信号可调制的PLL电路具有压控主振荡器，环路分频器，相位比较器和环路滤波器。 用于相位比较器的参考频率信号通过第一补偿滤波器，压控参考振荡器和参考分压器从调制信号导出，连接在所述第一补偿滤波器的下游。 压控主振荡器由调制信号经由第二补偿滤波器控制，随后是下行数据低通。

公开(公告)号：US5325075A

公开(公告)日：1994-06-28

申请号：US997285

申请日：1992-12-23

Applicant: Juha Rapeli

Inventor： Juha Rapeli

IPC: H03C3/00 ,  H03C3/09 ,  H04L27/20 ,  H04L27/36 ,  H03L7/18 ,  H03L7/22

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966

Abstract: The invention relates to a method, in which a phase modulated or frequency modulated signal can be directly generated with a PLL frequency synthesizer. With an interpolating synthesizer it is possible to create a very dense output frequency (f.sub.x) raster, so that the pulses received in the phase comparator (63) both from the reference signal (f.sub.o) branch and from the voltage controlled oscillator VCO (65) are lengthened in lengthening means (62, 69; 67, 68; k.sub.1, L+.DELTA.L; k.sub.2, L) by a desired amount. The numbers k.sub.1 and k.sub.2 are proportional to the amount of lengthening. When these integers now further are changed proportionally to the modulating signal, the change of the integers causes a change of the time difference of the pulses received by the phase comparator (63). This change of the time difference further causes a change in the output signal (f.sub.x) of the voltage controlled oscillator. The method is particularly well suited to provide digital quadrature phase modulation QPSK or quadrature amplitude modulation QAM, in which the shift from one carrier phase to another has a predetermined size and waveform as a function of time.

Abstract translation: 本发明涉及一种可以用PLL频率合成器直接产生相位调制或调频信号的方法。 通过内插合成器，可以创建非常密集的输出频率（fx）光栅，使得从参考信号（fo）支路和压控振荡器VCO（65）中接收的脉冲在相位比较器（63）中接收， 延长装置（62,69; 67,68; k1，L + DELTA L; k2，L）期望量。 数字k1和k2与延长量成比例。 当这些整数现在进一步与调制信号成比例地变化时，整数的改变引起由相位比较器（63）接收的脉冲的时间差的变化。 时间差的这种变化进一步导致压控振荡器的输出信号（fx）的变化。 该方法特别适用于提供数字正交相位调制QPSK或正交幅度调制QAM，其中从一个载波相位到另一个载波相位的移位具有作为时间的函数的预定大小和波形。

公开(公告)号：US5091706A

公开(公告)日：1992-02-25

申请号：US528654

申请日：1990-05-24

Applicant: Lloyd L. Lautzenhiser

Inventor： Lloyd L. Lautzenhiser

IPC: H03C3/09 ,  H03L7/193

CPC classification number: H03C3/0966 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03L7/193 ,  H03C2200/0079

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) and a radio frequency receiver (200) that utilizes the D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) both include a phase locking oscillator (70, 90, 128, 180, or 192) and a D.C. modulator (72, 92, 130, 156, 182, or 194). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C. modulation of the feedback path (16) optionally includes changing the frequency in the feedback path (16) as a function of the frequency of a modulation oscillator (64), changing the frequency in the feedback path (16) by a plurality of pulses for each cycle of the modulation oscillator (64), removing pulses from the feedback path (16), adding pulses to the feedback path (16), dividing the frequency in the feedback path (16) by higher and lower dividing ratios, preventing one cycle in the feedback path (16) from developing a " high" in the feedback path (16), and holding a "high" in the feedback path (16) between two adjacent pulses.

Abstract translation: 使用DC调制锁相振荡器（60,80,100,140,​​160或190）的DC调制锁相振荡器（60,80,100,140,​​160或190）和射频接收器（200） 两者都包括锁相振荡器（70,90,128,180或192）和DC调制器（72,92,130,156,182或194）。 正向路径（14）和反馈路径（16）都被调制。 反馈路径（16）的DC调制可选地包括根据调制振荡器（64）的频率来改变反馈路径（16）中的频率，将反馈路径（16）中的频率改变多个脉冲 对于调制振荡器（64）的每个周期，从反馈路径（16）去除脉冲，向反馈路径（16）添加脉冲，将反馈路径（16）中的频率除以更高和更低的分频比，防止一个 在反馈路径（16）中循环在反馈路径（16）中形成“高”，并且在两个相邻脉冲之间的反馈路径（16）中保持“高”。

公开(公告)号：US5038120A

公开(公告)日：1991-08-06

申请号：US486781

申请日：1990-03-01

Applicant: Mark A. Wheatley ,  Leslie A. Lepper ,  Nigel K. Webb

Inventor： Mark A. Wheatley ,  Leslie A. Lepper ,  Nigel K. Webb

IPC: H03C3/02 ,  H03C3/09 ,  H03L7/197

CPC classification number: H03C3/0991 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/1976 ,  H03C3/02

Abstract: A fractional-N type frequency synthesizer has a voltage controlled oscillator controlled in a phase-locked loop by a divide by N divider and a phase comparator responsive to the divided frequency and to a reference frequency Fr. An accumulator is responsive to the desired fractional part of the N and is clocked by Fr to produce carry signals for producing the required periodic variations in N. A second accumulator produces periodic equal and opposite further variations in N to reduce the magnitude of the error waveform which would be given to the phase-detector output by the variations in n caused by the first accumulator. A digital to analog converter and a differentiating circuit produce a jitter correction signal for reducing residual jitter. A coherent detector detects for the presence of any residual jitter at the control input of the VCO and resulting from the fractional-N control circuit. Any such residual jitter produces a control signal which adjusts the value of the jitter correction signal accordingly. Two-port frequency modulation is produced by an in-band circuit incorporating an integrator and a full band circuit. With no FM input, a counter detects any divergence in output frequency from the desired value and caused by spurious input at the integrator. A resultant control signal offsets any such spurious inputs. The coherent detector detects at the control input of the VCO any component which is coherent with the in band modulation signal and adjusts the full band modulation signal to eliminate this, so that correct FM is produced.

Abstract translation: 分数N型频率合成器具有通过除以N除法器和相位比较器在锁相环中控制的压控振荡器，该相位比较器响应于分频和参考频率Fr。 累加器响应于期望的N分数部分并由Fr计时，以产生用于产生N中所需的周期性变化的进位信号。第二个累加器在N中产生周期性相等和相反的其他变化，以减小误差波形的幅度 这将由由第一累加器引起的n的变化给予相位检测器输出。 数模转换器和微分电路产生抖动校正信号，以减少残余抖动。 相干检测器检测在VCO的控制输入处是否存在任何残留抖动，并由分数N控制电路产生。 任何这样的残余抖动产生相应地调整抖动校正信号的值的控制信号。 双端口频率调制由并入有积分器和全频带电路的带内电路产生。 在没有FM输入的情况下，计数器会从所需值检测输出频率的任何偏差，并由积分器的寄生输入引起。 所得到的控制信号抵消任何这样的虚假输入。 相干检测器在VCO的控制输入处检测与带内调制信号相干的任何分量，并调整全频带调制信号以消除该频带调制信号，从而产生正确的FM。

公开(公告)号：US4969210A

公开(公告)日：1990-11-06

申请号：US154550

申请日：1988-02-10

Applicant: Kenneth A. Hansen ,  Ralph T. Enderby

Inventor： Kenneth A. Hansen ,  Ralph T. Enderby

IPC: H04B1/40 ,  H03C3/09 ,  H03J5/02 ,  H03J5/24 ,  H04B1/16

CPC classification number: H03C3/0966 ,  H03C3/0941 ,  H03C3/0958 ,  H03J5/0272 ,  H03J5/242 ,  H04B1/16

Abstract: A method and arrangement for electronically bandswitching a radio (100) is described which includes at least a receiver (110, 111), a PLL (120), and a fully synchronized, programmable counter as a frequency divider (140) that is coupled between the receiver and the PLL. This fully synchronized divider (140) provides an output signal (143) at a lower frequency with minimal harmonic energy and improves the sideband noise performance as the divisor increases. When the radio also includes a transmitter (104), stepped attenuators (128, 132) are also included for adjusting the modulation of the PLL (120) when in the transmit mode.The PLL includes at least a reference signal generator (121, 122), a phase detector (124), and a voltage controlled oscillator (127) having an output (129) coupled, via a feedback path, to a second input (131) of the phase detector (124). The fully synchronized, programmable frequency divider includes at least a counter, a data loader, a half-period detector, and a synchronizer which are configured and arranged to provide an output signal (143) having a duty cycle, nearly equal to 50%, which is independent of a divisor and which simplifies the filtering requirements thereafter, thereby providing electronic bandswitching for the radio while exhibiting fast-locking and low-noise characteristics.

Abstract translation: 描述了一种用于电子频带切换无线电（100）的方法和装置，其包括至少一个接收机（110,111），PLL（120）和作为分频器（140）的完全同步的可编程计数器， 接收器和PLL。 这个完全同步的分压器（140）以较低频率提供具有最小谐波能量的输出信号（143），并且随着除数增加而改善边带噪声性能。 当无线电还包括发射机（104）时，还包括步进衰减器（128,132），用于在发射模式时调节PLL（120）的调制。 PLL包括至少参考信号发生器（121,122），相位检测器（124）和压控振荡器（127），其具有经由反馈路径耦合到第二输入端（131）的输出（129） 相位检测器（124）。 完全同步的可编程分频器至少包括计数器，数据加载器，半周期检测器和同步器，其被配置和布置成提供具有几乎等于50％的占空比的输出信号（143） 其独立于除数，并且此后简化了滤波要求，从而为显示快速锁定和低噪声特性的无线电提供电子频段切换。

公开(公告)号：US4743867A

公开(公告)日：1988-05-10

申请号：US80936

申请日：1987-08-03

Applicant: Joe M. Smith

Inventor： Joe M. Smith

IPC: H03C3/09 ,  H03C3/08 ,  H03L7/08

CPC classification number: H03C3/0975 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

Abstract: Phase port gain compensating circuitry is coupled to the phase modulation summing circuit and voltage controlled oscillator (VCO) gain compensating circuitry is coupled to the frequency control terminal of the VCO. Compensator control circuitry utilizes divider ratio control information to control the characteristics of the two compensators to compensate for otherwise undesirable effects on the phase-locked loop response parameters caused by changes in the divider ratio and in the VCO gain.

Abstract translation: 相位端口增益补偿电路耦合到相位调制求和电路，压控振荡器（VCO）增益补偿电路耦合到VCO的频率控制端。 补偿器控制电路利用分频比控制信息来控制两个补偿器的特性，以补偿由分频比和VCO增益的变化引起的对锁相环响应参数的不期望的影响。